ADSP-2181BST-133 Analog Devices Inc, ADSP-2181BST-133 Datasheet - Page 4

• Manufacturer Part Number: ADSP-2181BST-133
• Description: IC DSP CONTROLLER 16BIT 128TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2181BST-133

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 33.3MHz
• Non-volatile Memory: External
• On-chip Ram: 80kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 33.3MHz
• Mips: 33.3
• Device Input Clock Speed: 33.3MHz
• Ram Size: 80KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / RoHS Status: Not Compliant

ADSP-2181
• SPORTs support serial data word lengths from 3 to 16 bits
• SPORT receive and transmit sections can generate unique
• SPORTs can receive and transmit an entire circular buffer of
• SPORT0 has a multichannel interface to selectively receive
• SPORT1 can be configured to have two external interrupts
Pin Descriptions
The ADSP-2181 is available in 128-lead TQFP and 128-lead
PQFP packages.
Pin
Name(s)
Address
Data
RESET
IRQ2
IRQL0,
IRQL1
IRQE
BR
BG
BGH
PMS
DMS
BMS
IOMS
CMS
RD
WR
MMAP
BMODE
CLKIN,
XTAL
and provide optional A-law and -law companding according
to CCITT recommendation G.711.
interrupts on completing a data word transfer.
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
#
of
Pins
14
24
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
2
PIN FUNCTION DESCRIPTIONS
Input/
Output Function
O
I/O
I
I
I
I
I
O
O
O
O
O
O
O
O
O
I
I
I
Address Output Pins for Program,
Data, Byte, and I/O Spaces
Data I/O Pins for Program and
Data Memory Spaces (8 MSBs
Are Also Used as Byte Space
Addresses)
Processor Reset Input
Edge- or Level-Sensitive
Interrupt Request
Level-Sensitive Interrupt
Requests
Edge-Sensitive Interrupt
Request
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Program Memory Select Output
Data Memory Select Output
Byte Memory Select Output
I/O Space Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Memory Map Select Input
Boot Option Control Input
Clock or Quartz Crystal Input
–4–
Pin
Name(s)
CLKOUT 1
SPORT0
SPORT1
IRD, IWR 2
IS
IAL
IAD
IACK
PWD
PWDACK 1
FL0, FL1,
FL2
PF7:0
EE
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
GND
VDD
*These ADSP-2181 pins must be connected only to the EZ-ICE connector in
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2181 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and
FLAG_OUT, for a total of six external interrupts. The ADSP-
2181 also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power down and reset). The
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are level-
sensitive and IRQE is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.
the target system. These pins have no function except during emulation, and
do not require pull-up or pull-down resistors.
#
of
Pins
5
5
1
1
16
1
1
3
8
1
1
1
1
1
1
1
1
1
11
6
Input/
Output Function
O
I/O
I/O
I
I
I
I/O
O
I
O
O
I/O
*
*
*
*
*
*
*
*
*
–
–
Processor Clock Output
Serial Port I/O Pins
Serial Port 1 or Two External
IRQs, Flag In and Flag Out
IDMA Port Read/Write Inputs
IDMA Port Select
IDMA Port Address Latch
Enable
IDMA Port Address/Data Bus
IDMA Port Access Ready
Acknowledge
Power-Down Control
Power-Down Control
Output Flags
Programmable I/O Pins
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
Ground Pins
Power Supply Pins
REV. D