ADSP-2181BST-133 Analog Devices Inc, ADSP-2181BST-133 Datasheet - Page 5

• Manufacturer Part Number: ADSP-2181BST-133
• Description: IC DSP CONTROLLER 16BIT 128TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2181BST-133

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 33.3MHz
• Non-volatile Memory: External
• On-chip Ram: 80kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 33.3MHz
• Mips: 33.3
• Device Input Clock Speed: 33.3MHz
• Ram Size: 80KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / RoHS Status: Not Compliant

Source of Interrupt
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
The ADSP-2181 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. The stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.
The following instructions allow global enable or disable servic-
ing of the interrupts (including power down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The ADSP-2181 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
REV. D
Table I. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
Address (Hex)
–5–
Power-Down
The ADSP-2181 processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-
down features. For detailed information about the power-
down feature, refer to the ADSP-2100 Family User’s Manual,
Third Edition, “System Interface” chapter.
• Quick recovery from power-down. The processor begins
• Support for an externally generated TTL or CMOS
• Support for crystal operation includes disabling the oscil-
• Power-down is initiated by either the power-down pin
• Interrupt support allows an unlimited number of instruc-
• Context clear/save control allows the processor to con-
• The RESET pin also can be used to terminate power-
• Power-down acknowledge pin indicates when the proces-
Idle
When the ADSP-2181 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE instruction.
Slow Idle
The IDLE instruction is enhanced on the ADSP-2181 to let
the processor’s internal clock signal be slowed, further
reducing power consumption. The reduced clock fre-
quency, a programmable fraction of the normal clock rate,
is specified by a selectable divisor given in the IDLE in-
struction. The format of the instruction is
where n = 16, 32, 64 or 128. This instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor’s other internal
clock signals, such as SCLK, CLKOUT and timer clock,
are reduced by the same ratio. The default form of the
instruction, when no clock divisor is given, is the standard
IDLE instruction.
executing instructions in as few as 100 CLKIN cycles.
processor clock. The external clock can continue running
during power-down without affecting the lowest power
rating and 100 CLKIN cycle recovery.
lator to save power (the processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabi-
lize), and letting the oscillator run to allow 100 CLKIN
cycle start up.
(PWD) or the software power-down force bit.
tions to be executed before optionally powering down.
The power-down interrupt also can be used as a non-
maskable, edge-sensitive interrupt.
tinue where it left off or start with a clean context when
leaving the power-down state.
down.
sor has entered power-down.
IDLE (n);
ADSP-2181