ADSP-2181BST-133 Analog Devices Inc, ADSP-2181BST-133 Datasheet - Page 3

• Manufacturer Part Number: ADSP-2181BST-133
• Description: IC DSP CONTROLLER 16BIT 128TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2181BST-133

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 33.3MHz
• Non-volatile Memory: External
• On-chip Ram: 80kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 33.3MHz
• Mips: 33.3
• Device Input Clock Speed: 33.3MHz
• Ram Size: 80KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / RoHS Status: Not Compliant

ADSP-2181 can fetch an operand from program memory and
the next instruction in the same cycle.
In addition to the address and data bus for external memory
connection, the ADSP-2181 has a 16-bit Internal DMA port
(IDMA port) for connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with program-
mable wait state generation. External devices can gain control of
external buses with bus request/grant signals (BR, BGH and BG).
One execution mode (Go Mode) allows the ADSP-2181 to con-
tinue running from on-chip memory. Normal execution mode
requires the processor to halt while buses are granted.
The ADSP-2181 can respond to 13 possible interrupts, eleven
of which are accessible at any given time. There can be up to six
external interrupts (one edge-sensitive, two level-sensitive and
three configurable) and seven internal interrupts generated by
the timer, the serial ports (SPORTs), the Byte DMA port and
the power-down circuitry. There is also a master RESET signal.
The two serial ports provide a complete synchronous serial inter-
face with optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
REV. D
GENERATOR
ADDRESS
OUTPUT REGS
INPUT REGS
DATA
OUTPUT REGS
INPUT REGS
#1
ALU
ALU
GENERATOR
ADDRESS
DATA
#2
21xx CORE
DMD BUS
OUTPUT REGS
PMA BUS
DMA BUS
PMD BUS
INPUT REGS
OUTPUT REGS
INPUT REGS
MAC
MAC
16
R BUS
INSTRUCTION
REGISTER
SEQUENCER
PROGRAM
Figure 1. ADSP-2181 Block Diagram
OUTPUT REGS
INPUT REGS
SHIFTER
EXCHANGE
BUS
14
14
24
16
–3–
PROGRAM
16K
The ADSP-2181 provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycles, where n is a scaling value stored in an 8-bit regis-
ter (TSCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2181 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2181 SPORTs.
Refer to the ADSP-2100 Family User’s Manual, Third Edition for
further details.
• SPORTs are bidirectional and have a separate, double-
• SPORTs can use an external serial clock or generate their
• SPORTs have independent framing for the receive and trans-
SRAM
buffered transmit and receive section.
own serial clock internally.
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
TRANSMIT REG
24
RECEIVE REG
SERIAL
PORT 0
5
COMPANDING
ADSP-2181 INTEGRATION
16K
CIRCUITRY
DATA
SRAM
16
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
5
CONTROLLER
BYTE
DMA
TIMER
ADSP-2181
DMD
BUS
DMA BUS
PMA BUS
PMD BUS
PROGRAMMABLE
INTERRUPTS
CONTROL
POWER-
DOWN
LOGIC
FLAGS
I/O
INTERNAL
MUX
MUX
PORT
DMA
EXTERNAL
EXTERNAL
ADDRESS
DATA
14
BUS
BUS
2
3
8
4
16
24