EP2S30F672C3N Altera, EP2S30F672C3N Datasheet - Page 105

• Manufacturer Part Number: EP2S30F672C3N
• Description: IC STRATIX II FPGA 30K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S30F672C3N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 500
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• No. Of Macrocells: 33880
• Family Type: Stratix II
• No. Of I/o's: 500
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.6V
• Operating Frequency Max: 550MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1896; EP2S30F672C3N

Altera Corporation
May 2007
484-pin FineLine BGA
672-pin FineLine BGA
484-pin FineLine BGA
672-pin FineLine BGA
Table 2–21. EP2S15 Device Differential Channels
Table 2–22. EP2S30 Device Differential Channels
Package
Package
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
Transmitter
Receiver
device, PLL 1 can drive a maximum of 10 transmitter channels in I/O
bank 1 or a maximum of 19 transmitter channels in I/O banks 1 and 2. The
Quartus II software may also merge receiver and transmitter PLLs when
a receiver is driving a transmitter. In this case, one fast PLL can drive both
the maximum numbers of receiver and transmitter channels.
Transmitter/
Transmitter/
Receiver
Receiver
Channels
Channels
38
42
42
38
42
62
38
58
Total
Total
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Note (1)
Note (1)
PLL 1
PLL 1
10
19
11
21
10
19
11
21
10
19
11
21
16
29
17
31
Stratix II Device Handbook, Volume 1
PLL 2
PLL 2
Center Fast PLLs
Center Fast PLLs
19
10
21
19
10
21
19
10
21
13
29
14
31
9
9
9
Stratix II Architecture
PLL 3
PLL 3
19
10
21
19
10
21
19
10
21
13
29
14
31
9
9
9
PLL 4
PLL 4
10
19
11
21
10
19
11
21
10
19
11
21
16
29
17
31
2–97