EP2S30F672C3N Altera, EP2S30F672C3N Datasheet - Page 74

• Manufacturer Part Number: EP2S30F672C3N
• Description: IC STRATIX II FPGA 30K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S30F672C3N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 500
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• No. Of Macrocells: 33880
• Family Type: Stratix II
• No. Of I/o's: 500
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.6V
• Operating Frequency Max: 550MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1896; EP2S30F672C3N

PLLs & Clock Networks
2–66
Stratix II Device Handbook, Volume 1
c4
c5
Enhanced PLL 11 outputs
c0
c1
c2
c3
c4
c5
Clock pins
CLK4p
CLK5p
CLK6p
CLK7p
CLK4n
CLK5n
CLK6n
CLK7n
Drivers from internal logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
Top Side Global & Regional
Table 2–11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs
of 2)
Clock Network Connectivity
Table 2–12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL
Outputs
Regional Clock Network
Bottom Side Global &
Connectivity
(Part 1 of 2)
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Altera Corporation
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May 2007
(Part 2
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