EP1AGX90EF1152I6N Altera, EP1AGX90EF1152I6N Datasheet - Page 19

• Manufacturer Part Number: EP1AGX90EF1152I6N
• Description: IC ARRIA GX FPGA 90K 1152FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX90EF1152I6N

• Number Of Logic Elements/cells: 90220
• Number Of Labs/clbs: 4511
• Total Ram Bits: 4477824
• Number Of I /o: 538
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1152-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2387

Chapter 2: Arria GX Architecture
Transceivers
© December 2009 Altera Corporation
f
■
■
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The CRU controls whether the receiver PLL locks to the input reference clock
(lock-to-reference mode) or the incoming serial data (lock-to data mode). You can set
the CRU to switch between lock-to-data and lock-to-reference modes automatically or
manually. In automatic lock mode, the phase detector and dedicated parts per million
(PPM) detector within each receiver channel control the switch between lock-to-data
and lock-to-reference modes based on some pre-set conditions. In manual lock mode,
you can control the switch manually using the rx_locktorefclk and
rx_locktodata signals.
For more information, refer to the “Clock Recovery Unit” section in the
Transceiver Protocol Support and Additional Features
Table 2–4
and rx_locktodata signals.
Table 2–4. CRU Manual Lock Signals
If the rx_locktorefclk and rx_locktodata ports are not used, the default
setting is automatic lock mode.
Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the
high-speed serial recovered clock and deserializes into 8- or 10-bit parallel data using
the low-speed parallel recovered clock. The serial data is assumed to be received with
LSB first, followed by MSB. It feeds the deserialized 8- or 10-bit data to the word
aligner, as shown in
The voltage-controlled oscillator (V
Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and 25. Not all
settings are supported for any particular frequency.
Two lock indication signals are provided. They are found in PFD mode
(lock-to-reference clock), and PD (lock-to-data).
rx_locktorefclk
lists the behavior of the CRU block with respect to the rx_locktorefclk
1
0
x
Figure
2–14.
rx_locktodata
0
1
0
CO
) operates at half rate.
chapter.
Lock-to-reference clock
Lock-to-data
Automatic
Arria GX Device Handbook, Volume 1
CRU Mode
Arria GX
2–13