EP2SGX60EF1152C5N Altera, EP2SGX60EF1152C5N Datasheet - Page 161

• Manufacturer Part Number: EP2SGX60EF1152C5N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C5N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2185

Altera Corporation
October 2007
f
The nIO_PULLUP pin is a dedicated input that chooses whether the
internal pull-up resistors on the user I/O pins and dual-purpose
configuration I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY,
nCS, CS, RUnLU, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR)
are on or off before and during configuration. A logic high (1.5, 1.8, 2.5,
3.3 V) turns off the weak internal pull-up resistors, while a logic low turns
them on.
Stratix II GX devices also offer a new power supply, V
be connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available
on the configuration input pins and JTAG pins. V
JTAG input pins (TCK, TMS, TDI, and TRST) and the following
configuration pins: nCONFIG, DCLK (when used as an input),
nIO_PULLUP, DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and
CLKUSR. The VCCSEL pin allows the V
configuration inputs reside) to be independent of the voltage required by
the configuration inputs. Therefore, when selecting the V
you do not have to take the V
inputs into consideration. The configuration input pins, nCONFIG, DCLK
(when used as an input), nIO_PULLUP, RUnLU, nCE, nWS, nRS, CS, nCS,
and CLKUSR, have a dual buffer design: a 3.3-V/2.5-V input buffer and a
1.8-V/1.5-V input buffer. The V
is used. The 3.3-V/2.5-V input buffer is powered by V
V/1.5-V input buffer is powered by V
V
change on-the-fly or during a reconfiguration. The V
powered by V
high V
selects the 3.3-V/2.5-V input buffer. V
the logic levels driven out of the configuration device or the MAX II
microprocessor.
If the design must support configuration input voltages of 3.3 V/2.5 V, set
V
contains the configuration inputs to any supported voltage. If the design
must support configuration input voltages of 1.8 V/1.5 V, set V
logic high and the V
inputs to 1.8 V/1.5 V.
For more information on multi-volt support, including information on
using TDO and nCEO in multi-volt systems, refer to the
Architecture
CCSEL
CCSEL
CCSEL
is sampled during power-up. Therefore, the V
to a logic low. You can set the V
chapter in volume 1 of the Stratix II GX Device Handbook.
connection selects the 1.8-V/1.5-V input buffer; a logic low
CCINT
and must be hardwired to V
CCIO
of the bank that contains the configuration
IL
and V
CCSEL
Stratix II GX Device Handbook, Volume 1
input pin selects which input buffer
IH
CCIO
CCSEL
CCIO
CCIO
levels driven to the configuration
.
setting (of the banks where the
should be set to comply with
voltage of the I/O bank that
CCPD
CCPD
Configuration & Testing
CCSEL
CCSEL
or ground. A logic
CCPD
CCPD
applies to all the
Stratix II GX
CCIO
input buffer is
, while the 1.8-
setting cannot
, which must
voltage,
CCSEL
to a
3–5