EP2SGX60EF1152C5N Altera, EP2SGX60EF1152C5N Datasheet - Page 34

• Manufacturer Part Number: EP2SGX60EF1152C5N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C5N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2185

Transceivers
2–26
Stratix II GX Device Handbook, Volume 1
GIGE Mode
In GIGE mode, the rate matcher adheres to the specifications in clause 36
of the IEEE 802.3 documentation for idle additions or removals. The rate
matcher performs clock compensation only on /I2/ ordered sets,
composed of a /K28.5/+ followed by a /D16.2/-. The rate matcher does
not perform clock compensation on any other ordered set combinations.
An /I2/ is added or deleted automatically based on the number of words
in the FIFO buffer. A K28.4 is given at the control and data ports when the
FIFO buffer is in an overflow or underflow condition.
XAUI Mode
In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae
specification for clock rate compensation. The rate matcher performs
clock compensation on columns of /R/ (/K28.0/), denoted by //R//.
An //R// is added or deleted automatically based on the number of
words in the FIFO buffer.
PCI Express Mode
PCI Express mode operates at a data rate of 2.5 Gbps, and supports lane
widths of ×1, ×2, ×4, and ×8. The rate matcher can support up to
± 300-PPM differences between the upstream transmitter and the
receiver. The rate matcher looks for the skip ordered sets (SOS), which
usually consist of a /K28.5/ comma followed by three /K28.0/ skip
characters. The rate matcher deletes or inserts skip characters when
necessary to prevent the rate matching FIFO buffer from overflowing or
underflowing.
The Stratix II GX rate matcher in PCI Express mode has FIFO overflow
and underflow protection. In the event of a FIFO overflow, the rate
matcher deletes any data after the overflow condition to prevent FIFO
pointer corruption until the rate matcher is not full. In an underflow
condition, the rate matcher inserts 9'h1FE (/K30.7/) until the FIFO is not
empty. These measures ensure that the FIFO can gracefully exit the
overflow and underflow condition without requiring a FIFO reset.
8B/10B Decoder
The 8B/10B decoder
digital blocks (PCS) and lies in the receiver path between the rate matcher
and the byte deserializer blocks. The 8B/10B decoder operates in
single-width and double-width modes, and can be bypassed if the
8B/10B decoding is not necessary. In single-width mode, the 8B/10B
decoder restores the 8-bit data + 1-bit control identifier from the 10-bit
code. In double-width mode, there are two 8B/10B decoders in parallel,
which restores the 16-bit (2 × 8-bit) data + 2-bit (2 × 1-bit) control identifier
from the 20-bit (2 × 10-bit) code. This 8B/10B decoder conforms to the
IEEE 802.3 1998 edition standards.
(Figure
2–21) is part of the Stratix II GX transceiver
Altera Corporation
October 2007