EP2SGX60EF1152C5N Altera, EP2SGX60EF1152C5N Datasheet - Page 83

• Manufacturer Part Number: EP2SGX60EF1152C5N
• Description: IC STRATIX II GX 60K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX60EF1152C5N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 534
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 534
• Frequency (max): 609.76MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2185

Figure 2–52. M4K RAM Block LAB Row Interface
Altera Corporation
October 2007
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnect
M4K RAM Block Local
Interconnect Region
16
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■
■
■
■
You cannot use an initialization file to initialize the contents of a M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed.
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
datain
control
signals
clocks
LAB Row Clocks
M4K RAM
address
Block
dataout
byte
enable
36
Stratix II GX Device Handbook, Volume 1
6
Stratix II GX Architecture
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnect
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