IC APEX 20KE FPGA 100K 208-PQFP

 

EP20K100EQC208-3

Manufacturer Part NumberEP20K100EQC208-3
DescriptionIC APEX 20KE FPGA 100K 208-PQFP
ManufacturerAltera
SeriesAPEX-20K®
EP20K100EQC208-3 datasheets

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Specifications of EP20K100EQC208-3

Number Of Logic Elements/cells4160Number Of Labs/clbs416
Total Ram Bits53248Number Of I /o151
Number Of Gates263000Voltage - Supply1.71 V ~ 1.89 V
Mounting TypeSurface MountOperating Temperature0°C ~ 85°C
Package / Case208-MQFP, 208-PQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-2092  
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Page 43/117

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Figure 28. Column IOE Connection to the Interconnect
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
Row Interconnect
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Figure 28
shows how a column IOE connects to the interconnect.
Each IOE can drive column interconnect. In APEX 20KE devices,
IOEs can also drive FastRow interconnect. Each IOE data
and OE signal is driven by local interconnect.
IOE
LAB
MegaLAB Interconnect
Dedicated Fast I/O Pins
APEX 20KE devices incorporate an enhancement to support bidirectional
pins with high internal fanout such as PCI control signals. These pins are
called Dedicated Fast I/O pins (FAST1, FAST2, FAST3, and FAST4) and
replace dedicated inputs. These pins can be used for fast clock, clear, or
high fanout logic signal distribution. They also can drive out. The
Dedicated Fast I/O pin data output and tri-state control are driven by
local interconnect from the adjacent MegaLAB for high speed.
IOE
Column Interconnect
43

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