EP4CE55F23I7 Altera, EP4CE55F23I7 Datasheet - Page 365

• Manufacturer Part Number: EP4CE55F23I7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Top-Level Port Lists
Table 1–29. Multipurpose PLL, General Purpose PLL and Miscellaneous Ports in ALTGX Megafunction for
Cyclone IV GX (Part 2 of 2)
© December 2010 Altera Corporation
Reset &
Power
Down
Reconfigu
ration
Calibration
Block
Test Mode
Block
gxb_powerdown
tx_digitalreset
rx_analogreset
rx_digitalreset
reconfig_clk
reconfig_togxb
reconfig_fromgxb
cal_blk_clk
cal_blk_powerdown
rx_bistdone
rx_bisterr
Port Name
Output
Input
Input
Input
Input
Input
Input
Output
Input
Input
Output
Output
Input/
Asynchronous signal
Asynchronous signal.
The minimum pulse
width is two parallel
clock cycles.
Asynchronous signal.
The minimum pulse
width is two parallel
clock cycles.
Asynchronous signal.
The minimum pulse
width is two parallel
clock cycles.
Clock signal
Asynchronous signal
Asynchronous signal
Clock signal
Asynchronous signal
Asynchronous signal
Asynchronous signal
Clock Domain
Transceiver block power down.
■
■
Transmitter PCS reset.
■
Receiver PMA reset.
■
Receiver PCS reset.
■
Dynamic reconfiguration clock.
■
■
From the dynamic reconfiguration controller.
To the dynamic reconfiguration controller.
Clock for the transceiver calibration block.
Calibration block power down control.
BIST or PRBS test completion indicator.
■
■
BIST or PRBS verifier error indicator
■
■
When asserted, all digital and analog circuitry in the PCS,
HSSI, CDR, and PCIe modules are powered down.
Asserting the gxb_powerdown signal does not power down
the refclk buffers.
When asserted, the transmitter PCS blocks are reset.
When asserted, analog circuitry in the receiver PMA block is
reset.
When asserted, the receiver PCS blocks are reset.
Also used for offset cancellation except in PIPE mode.
For the supported frequency range for this clock, refer to
Cyclone IV Device Data Sheet
A high level during BIST test mode indicates the verifier either
receives complete pattern cycle or detects an error and stays
asserted until being reset using the rx_digitalreset
port.
A high level during PRBS test mode indicates the verifier
receives complete pattern cycle and stays asserted until being
reset using the rx_digitalreset port.
In BIST test mode, the signal stays asserted upon detecting an
error until being reset using the rx_digitalreset port.
In PRBS test mode, the signal asserts for a minimum of 3
rx_clkout clock cycles upon detecting an error and
deasserts if the following PRBS sequence contains no error.
Cyclone IV Device Handbook, Volume 2
Description
chapter.
1–85
the