EP4CE55F23I7 Altera, EP4CE55F23I7 Datasheet - Page 86

• Manufacturer Part Number: EP4CE55F23I7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–24
Normal Mode
Cyclone IV Device Handbook, Volume 1
An internal clock in normal mode is phase-aligned to the input clock pin. The external
clock output pin has a phase delay relative to the clock input pin if connected in this
mode. The Quartus II software timing analyzer reports any phase difference between
the two. In normal mode, the PLL fully compensates the delay introduced by the
GCLK network.
Figure 5–14
this mode.
Figure 5–14. Phase Relationship Between PLL Clocks in Normal Mode
Note to
(1) The external clock output can lead or lag the PLL internal clock signals.
Figure
5–14:
shows a waveform example of the phase relationship of the PLL clocks in
PLL Reference
Clock at the Input pin
PLL Clock at the
Register Clock Port
External PLL Clock
Outputs
(1)
Phase Aligned
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
© December 2010 Altera Corporation
Clock Feedback Modes