EP4CE55F23I7 Altera, EP4CE55F23I7 Datasheet - Page 393

• Manufacturer Part Number: EP4CE55F23I7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Controller Port List
Dynamic Reconfiguration Controller Port List
Table 3–2. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 1 of 6)
© December 2010 Altera Corporation
Clock Inputs to ALTGX_RECONFIG Instance
reconfig_clk
ALTGX and ALTGX_RECONFIG Interface Signals
reconfig_fromgxb
[n..0]
reconfig_togxb
[3..0]
Port Name
Table 3–2
reconfiguration controller.
Output
Output
Input/
Input
Input
lists the input control ports and output status ports of the dynamic
The frequency range of this clock depends on the following transceiver channel configuration
modes:
■
■
■
By default, the Quartus
be a free-running clock sourced from an I/O clock pin. Do not use dedicated transceiver REFCLK
pins or any clocks generated by transceivers.
An output port in the ALTGX instance and an input port in the ALTGX_RECONFIG instance. This
signal is transceiver-block based. Therefore, the width of this signal increases in steps of 5 bits
per transceiver block.
In the ALTGX MegaWizard Plug-In Manager, the width of this signal depends on the number of
channels you select in the What is the number of channels? option in the General screen.
For example, if you select the number of channels in the ALTGX instance as follows:
1  Channels  4, then the output port reconfig_fromgxb[4..0] = 5 bits
5  Channels  8, then the output port reconfig_fromgxb[9..0] = 10 bits
9  Channels  12, then the output port reconfig_fromgxb[14..0] = 15 bits
13  Channels  16, then the output port reconfig_fromgx[19..0] = 20 bits
To connect the reconfig_fromgxb port between the ALTGX_RECONFIG instance and
multiple ALTGX instances, follow these rules:
■
■
The Quartus II Fitter produces a warning if the dynamic reconfiguration option is enabled in the
ALTGX instance but the reconfig_fromgxb and reconfig_togxb ports are not
connected to the ALTGX_RECONFIG instance.
An input port of the ALTGX instance and an output port of the ALTGX_RECONFIG instance. You
must connect the reconfig_togxb[3..0] input port of every ALTGX instance controlled
by the dynamic reconfiguration controller to the reconfig_togxb[3..0] output port of
the ALTGX_RECONFIG instance.
The width of this port is always fixed to 4 bits.
Receiver only (37.5 MHz to 50 MHz)
Receiver and Transmitter (37.5 MHz to 50 MHz)
Transmitter only (2.5 MHz to 50 MHz)
Connect the reconfig_fromgxb[4..0] of ALTGX Instance 1 to the
reconfig_fromgxb[4..0] of the ALTGX_RECONFIG instance. Connect the
reconfig_fromgxb[] port of the next ALTGX instance to the next available bits of the
ALTGX_RECONFIG instance, and so on.
Connect the reconfig_fromgxb port of the ALTGX instance, which has the highest
What is the starting channel number? option, to the MSB of the reconfig_fromgxb
port of the ALTGX_RECONFIG instance.
®
II software assigns a global clock resource to this port. This clock must
Description
Cyclone IV Device Handbook, Volume 2
3–3