EP4CE55F23I7 Altera, EP4CE55F23I7 Datasheet - Page 76

• Manufacturer Part Number: EP4CE55F23I7
• Description: IC CYCLONE IV FPGA 55K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV Er

Specifications of EP4CE55F23I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2340000
• Number Of I /o: 324
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

5–14
Cyclone IV Device Handbook, Volume 1
From the clock sources listed above, only two clock input pins, two out of four PLL
clock outputs (two clock outputs from either adjacent PLLs), one DPCLK pin, and one
source from internal logic can drive into any given clock control block, as shown in
Figure 5–1 on page
Out of these six inputs to any clock control block, the two clock input pins and two
PLL outputs are dynamically selected to feed a GCLK. The clock control block
supports static selection of the signal from internal logic.
Figure 5–5
Cyclone IV GX device periphery.
Figure 5–5. Clock Control Blocks on Each Side of Cyclone IV GX Device
Notes to
(1) The EP4CGX15 device has two DPCLK pins; the EP4CGX22 and EP4CGX30 devices have four DPCLK pins; the
(2) Each clock control block in the EP4CGX15, EP4CGX22, and EP4CGX30 devices can drive five GCLK networks. Each
The inputs to the five clock control blocks on each side of the Cyclone IV E device
must be chosen from among the following clock sources:
■
■
■
■
From the clock sources listed above, only two clock input pins, two PLL clock outputs,
one DPCLK or CDPCLK pin, and one source from internal logic can drive into any
given clock control block, as shown in
Out of these six inputs to any clock control block, the two clock input pins and two
PLL outputs are dynamically selected to feed a GCLK. The clock control block
supports static selection of the signal from internal logic.
Figure 5–6
the Cyclone IV E device periphery.
Three or four clock input pins, depending on the specific device
Five PLL counter outputs
Two DPCLK pins and two CDPCLK pins from both the left and right sides and four
DPCLK pins from both the top and bottom
Five signals from internal logic
EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices have six DPCLK pins.
clock control block in the EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices can drive six GCLK
networks.
Figure
shows a simplified version of the clock control blocks on each side of the
shows a simplified version of the five clock control blocks on each side of
5–5:
5–10.
Clock Input Pins
Internal Logic
PLL Outputs
DPCLK (1)
2, 4, or 6
10
4
5
Five or six clock control
Figure 5–1 on page
blocks on each side
of the device
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Control
Clock
Block
5 or 6 (2)
© December 2010 Altera Corporation
5–10.
GCLK
Clock Networks