EP1SGX40DF1020C6N Altera, EP1SGX40DF1020C6N Datasheet - Page 12

• Manufacturer Part Number: EP1SGX40DF1020C6N
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40DF1020C6N

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Figure 2–1. Stratix GX Transceiver Block
Notes to
(1)
(2)
2–2
Stratix GX Device Handbook, Volume 1
Each receiver channel has its own PLL and CRU, which are not shown in this diagram. For more information, refer
to the section
For possible transmitter PLL clock inputs, refer to the section
Logic
Array
Logic
Array
Logic
Array
Logic
Array
Logic
Array
PLD
PLD
PLD
PLD
PLD
Figure
2–1:
“Receiver Path” on page
Receiver
Machine
State
XAUI
Transmitter
Machine
2–13.
State
Transmitter Channel 0
Transmitter Channel 1
XAUI
Transmitter Channel 2
Transmitter Channel 3
Receiver Channel 0
Receiver Channel 1
Receiver Channel 2
Receiver Channel 3
Note (1)
Channel 0
Channel 1
Channel 2
Channel 3
Channel
Machine
Aligner
State
“Transmitter Path” on page
Transmitter
PLL
2–5.
Altera Corporation
Receiver Pins
Transmitter Pins
Receiver Pins
Transmitter Pins
Receiver Pins
Transmitter Pins
Receiver Pins
Transmitter Pins
Logic
Array
PLD
(2)
June 2006