EP1SGX40DF1020C6N Altera, EP1SGX40DF1020C6N Datasheet - Page 24

• Manufacturer Part Number: EP1SGX40DF1020C6N
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40DF1020C6N

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Stratix GX Device Handbook, Volume 1
Figure 2–10
■
■
Figure 2–10. Receiver Input Buffer
Programmable Termination
The programmable termination can be statically set in the Quartus II
software.
termination.
Figure 2–11. Programmable Receiver Termination
If you use external termination, then the receiver must be externally
terminated and biased to 1.1 V.
external termination/biasing circuit.
Input
Pins
Programmable termination
Programmable equalizer
Figure 2–11
Programmable
shows a diagram of the receiver input buffer, which contains:
Termination
50, 60, or 75 Ω
50, 60, or 75 Ω
shows the setup for programmable receiver
Programmable
Figure 2–12
Equalizer
V
CM
shows an example of an
Differential
Altera Corporation
Buffer
Input
Differential
June 2006
Buffer
Input