EP1SGX40DF1020C6N Altera, EP1SGX40DF1020C6N Datasheet - Page 265

• Manufacturer Part Number: EP1SGX40DF1020C6N
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40DF1020C6N

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
June 2006
t
t
t
t
t
t
t
f
t
t
f
% spread
t
f
f
f
t
t
t
OUTDUTY
JITTER
CONFIG5,6
CONFIG11,12
SCANCLK
DLOCK
LOCK
VCO
LSKEW
SKEW
SS
ARESET
IN
INDUTY
EINDUTY
INJITTER
EINJITTER
FCOMP
Table 6–88. Enhanced PLL Specifications for -5 Speed Grades (Part 2 of 2)
Table 6–89. Enhanced PLL Specifications for -6 Speed Grades
Symbol
Symbol
Duty cycle for external clock output
(when set to 50%)
Period jitter for external clock output
Time required to reconfigure the scan
chains for PLLs 5 and 6
Time required to reconfigure the scan
chains for PLLs 11 and 12
scanclk frequency
Time required to lock dynamically (after
switchover or reconfiguring any non-
post-scale counters/delays)
Time required to lock from end of
device configuration
PLL internal VCO operating range
Clock skew between two external clock
outputs driven by the same counter
Clock skew between two external clock
outputs driven by the different counters
with the same settings
Spread spectrum modulation frequency
Percentage spread for spread
spectrum frequency
Minimum pulse width on
signal
Input clock frequency
Input clock duty cycle
External feedback clock input duty
cycle
Input clock period jitter
External feedback clock period jitter
External feedback clock compensation
time
(3)
Parameter
Parameter
(9)
(4)
areset
(6)
(5)
3
Min Typ
Min Typ
300
0.4
40
40
45
10
30
10
(1)
±50
±75
0.5
(Part 1 of 2)
±20 mUI for <200 MHz outclk
Stratix GX Device Handbook, Volume 1
±100 ps for >200 MHz outclk
DC & Switching Characteristics
289/f
193/f
±200
±200
800
Max
Max
650
100
400
150
0.6
60
60
55
SCANCLK
SCANCLK
22
6
(7)
(2)
(2)
ps or
MHz
MHz
MHz
Unit
Unit
mUI
kHz
ps
ps
ns
6–63
μs
μs
ps
ps
ns
%
%
%
%