EP1S60F1020C6 Altera, EP1S60F1020C6 Datasheet - Page 124

• Manufacturer Part Number: EP1S60F1020C6
• Description: IC STRATIX FPGA 60K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S60F1020C6

• Number Of Logic Elements/cells: 57120
• Number Of Labs/clbs: 5712
• Total Ram Bits: 5215104
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1433; EP1S60F1020C6

I/O Structure
Figure 2–64. Stratix IOE in Bidirectional I/O Configuration
Note to
(1)
2–110
Stratix Device Handbook, Volume 1
Column or Row
Interconnect
All input signals to the IOE can be inverted at the IOE.
I/O Interconnect
Figure
[15..0]
2–64:
ioe_clk[7..0]
OE
clkout
ce_out
aclr/prn
clkin
ce_in
sclr/preset
The Stratix device IOE includes programmable delays that can be
activated to ensure zero hold times, input IOE register-to-logic array
register transfers, or logic array-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay. Programmable
delays exist for decreasing input-pin-to-logic-array and IOE input
register delays. The Quartus II Compiler can program these delays to
automatically minimize setup time while providing a zero hold time.
Programmable delays can increase the register-to-pin delays for output
Chip-Wide Reset
Register Delay
Logic Array
Enable Clock
Enable Delay
Enable Delay
Output Clock
to Output
Output
Enable Delay
Input Clock
Output Register
Input Register
OE Register
D
ENA
CLRN/PRN
ENA
D
ENA
CLRN/PRN
D
CLRN/PRN
Note (1)
Q
Q
Q
Drive Strength Control
Pin Delay
Output
Open-Drain Output
Input Register Delay
Logic Array Delay
Slew Control
Input Pin to
Input Pin to
t
ZX
Output
Delay
OE Register
t
CO
Delay
V
CCIO
Altera Corporation
Optional
PCI Clamp
V
CCIO
Bus-Hold
Circuit
July 2005
Programmable
Pull-Up
Resistor