EP1S60F1020C6 Altera, EP1S60F1020C6 Datasheet - Page 243

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EP1S60F1020C6

Manufacturer Part Number
EP1S60F1020C6
Description
IC STRATIX FPGA 60K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S60F1020C6

Number Of Logic Elements/cells
57120
Number Of Labs/clbs
5712
Total Ram Bits
5215104
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1433
EP1S60F1020C6

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Altera Corporation
January 2006
Decrease input delay
to internal cells
Decrease input delay
to input register
Decrease input delay
to output register
Increase delay to
output pin
Increase delay to
output enable pin
Increase output clock
enable delay
Increase input clock
enable delay
Increase output
enable clock enable
delay
Increase t
output pin
Table 4–109. Stratix IOE Programmable Delays on Column Pins
Parameter
ZX
delay to
Off
Small
Medium
Large
On
Off
On
Off
On
Off
On
Off
On
Off
Small
Large
On
Off
Small
Large
On
Off
Small
Large
On
Off
On
Setting
Tables 4–109
IOE programmable delays. These delays are controlled with the
Quartus II software logic options listed in the Parameter column.
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Min
3,970
3,390
2,810
3,900
1,240
1,016
1,016
1,016
1,016
1,016
1,016
2,199
and
Max
224
224
397
338
540
540
540
0
0
0
0
0
0
0
0
4–110
Min
show the adder delays for the column and row
4,367
3,729
3,091
4,290
1,364
1,118
1,118
1,118
1,118
1,118
1,118
2,309
Max
235
235
417
372
594
594
594
0
0
0
0
0
0
0
0
Note (1)
Min
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
5,022
4,288
3,554
4,933
1,568
1,285
1,285
1,285
1,285
1,285
1,285
2,309
Max
270
270
417
427
683
683
683
0
0
0
0
0
0
0
0
Min
5,908
5,045
4,181
5,804
1,845
1,512
1,512
1,512
1,512
1,512
1,512
2,309
Max
318
318
417
503
804
804
804
0
0
0
0
0
0
0
0
Unit
4–73
ps
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