XE8801AMI027LF Semtech, XE8801AMI027LF Datasheet - Page 78

IC DAS 16BIT FLASH 8K MTP 44LQFP

XE8801AMI027LF

Manufacturer Part Number
XE8801AMI027LF
Description
IC DAS 16BIT FLASH 8K MTP 44LQFP
Manufacturer
Semtech
Datasheet

Specifications of XE8801AMI027LF

Applications
Sensing Machine
Core Processor
RISC
Program Memory Type
FLASH (22 kB)
Controller Series
XE8000
Ram Size
512 x 8
Interface
UART, USRT
Number Of I /o
24
Voltage - Supply
2.4 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-LQFP
For Use With
XE8000MP - PROG BOARD AND PROSTART2 CARD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XE8801AMI027LF
Manufacturer:
Semtech
Quantity:
10 000
14.6.3
On detection of the start bit, the UartRxBusy bit is set. On detection of the stop bit, the received data are
transferred from the internal shift register to the register RegUartRx. At the same time, the UartRxFull bit is set
and an interrupt is generated on Irq_uart_Rx. This indicates that new data is available in RegUartRx. The timing
diagram is shown in Figure 14-2.
The UartRxFull bit is cleared when RegUartRx is read. If the register was not read before the receiver transfers a
new word to it, the bit UartRxOErr (overflow error) is set and the previous contents of the register is lost.
UartRxOErr is cleared by writing any data to RegUartRxSta.
The bit UartRxSErr is set if a start error has been detected. The bit is updated at data transfer to RegUartRx.
The bit UartRxPErr is set if a parity error has been detected, i.e. the received parity bit is not equal to the
calculated parity of the received data. The bit is updated at data transfer to RegUartRx.
The bit UartRxFErr in RegUartRxSta shows that a frame error has been detected. No stop bit has been detected.
Figure 14-2. Uart reception timing diagram.
14.7 Interrupt or polling
The transmission and reception software can be driven by interruption or by polling the status bits.
Interrupt driven reception: each time an Irq_uart_Rx interrupt is generated, a new word is available in RegUartRx.
The register has to be read before a new word is received.
Interrupt driven transmission: each time the contents of RegUartTx is transferred to the transmission shift register,
an Irq_uart_Tx interrupt is generated. A new word can then be written to RegUartTx.
Reception driven by polling: the UartRxFull bit is to be read and checked. When it is 1, the RegUartRx register
contains new data and has to be read before a new word is received.
Transmission driven by polling: the UartTxFull bit is to read and checked. When it is 0, the RegUartTx register is
empty and a new word can be written to it.
© Semtech 2005
Asynchronous Reception
read of RegUartRx (software)
reguartrx_shift
Reception
UartRxBusy
RegUartRx
Irq_uart_Rx
UartRxFull
shift clock
Rx
start
b0
14-6
b6/7
parity
stop
word 1
XE8801A – SX8801R
word 1
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