Manufacturer Part NumberCY7C63001A-PXC
DescriptionIC MCU 4K USB MCU LS 20-DIP
ManufacturerCypress Semiconductor Corp
CY7C63001A-PXC datasheet

Specifications of CY7C63001A-PXC

ApplicationsUSB MicrocontrollerCore ProcessorM8A
Program Memory TypeOTP (4 kB)Controller SeriesCY7C630xx
Ram Size128 x 8InterfaceUSB
Number Of I /o12Voltage - Supply4 V ~ 5.25 V
Operating Temperature0°C ~ 70°CMounting TypeThrough Hole
Package / Case20-DIP (0.300", 7.62mm)Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other names428-1616  
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• Low-cost solution for low-speed USB peripherals such
as mouse, joystick, and gamepad
• USB Specification Compliance
— Conforms to USB 1.5-Mbps Specification,
Version 1.1
— Supports one device address and two endpoints
(one control endpoint and one data endpoint)
• 8-bit RISC microcontroller
— Harvard architecture
— 6-MHz external ceramic resonator
— 12-MHz internal operation
— USB optimized instruction set
• Internal memory
— 128 bytes of RAM
— 4 Kbytes of EPROM
Logic Block Diagram
2/4 KByte
on Reset
Cypress Semiconductor Corporation
Document #: 38-08026 Rev. *A
Universal Serial Bus Microcontroller
— Integrated USB transceiver
— Up to 16 Schmitt trigger I/O pins with internal pull-up
— Up to eight I/O pins with LED drive capability
— Special purpose I/O mode supports optimization of
photo transistor and LED in mouse application
— Maskable Interrupts on all I/O pins
• 8-bit free-running timer
• Watchdog timer (WDT)
• Internal power-on reset (POR)
• Instant-On Now™ for Suspend and Periodic Wake-up
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.25 VDC
• Operating temperature from 0–70°C
• Available in space saving and low-cost 20-pin PDIP,
20-pin SOIC, and 24-pin QSOP packages
• Industry-standard programmer support
3901 North First Street
San Jose
CA 95134
Revised October 5, 2004

CY7C63001A-PXC Summary of contents

  • Page 1

    ... SOIC, and 24-pin QSOP packages • Industry-standard programmer support R/C EXT INSTANT-ON RAM NOW™ 128-Byte USB PORT 0 Engine P0.0–P0.7 D+,D– • 3901 North First Street CY7C63001A CY7C63101A 8-bit Timer PORT 1 P1.0–P1.7 , • San Jose CA 95134 • 408-943-2600 Revised October 5, 2004 ...

  • Page 2

    ... Port 0 bit Port 0 bit Port 0 bit Port 0 bit Port 0 bit Port 1 bit Port 1 bit Port 1 bit Port 1 bit Port 1 bit Port 1 bit Port 1 bit Port 1 bit Ceramic resonator Ceramic resonator out CY7C63001A CY7C63101A CY7C63101A DIE SOIC (-SC) packages. The Description Page 26-GPIO ...

  • Page 3

    ... Ground Description 6.1.1 Program Memory Organization The CY7C63001A and CY7C63101A each offer 4 Kbytes of EPROM. The program memory space is divided into two functional groups: interrupt vectors and program code. The interrupt vectors occupy the first 16 bytes of the program space. Each vector is 2 bytes long. After a reset, the Program Counter points to location zero of the program space ...

  • Page 4

    ... On-chip program Memory 0x07FF 2K ROM (CY7C63000A, CY7C63100A) 0x0FFF 4K ROM (CY7C63001A, CY7C63101A) Figure 6-1. Program Memory Space The DSP pre-decrements by one whenever a PUSH instruction is executed and it increments by one after a POP instruction is used. The default value of the DSP after reset is 0x00, which would cause the first PUSH to write into USB FIFO space for Endpoint 1 ...

  • Page 5

    ... Input sink current control for Port 0 pins. There is one Isink register for each pin. Address of the Isink register for pin 0 is located at 0x30 and the register address for pin 7 is located at 0x37. CY7C63001A CY7C63101A USB FIFO – Endpoint 0 USB FIFO – Endpoint 1 ...

  • Page 6

    ... POR to conserve power (the clock oscillator, the timers, and the interrupt logic are turned off in suspend mode). After POR, only a non-idle USB Bus state terminates the suspend mode. The microcontroller then begins execution from ROM address 0x00. CY7C63001A CY7C63101A Function Figure 6-13 Figure 6-3 ...

  • Page 7

    ... C timing circuit. The format of the Cext register is shown in Figure 6-5. Reading the register returns the value of the Cext pin. During a reset, the Cext pin is HIGH Reserved Reserved Figure 6-5. The Cext Register (Address 0x22) CY7C63001A CY7C63101A Execution begins at Reset Vector 0x00 b2 b1 Reserved Reserved 0 0 Page ...

  • Page 8

    ... P0.5 P0.4 P0.3 R/W R/W R Figure 6-8. Port 0 Data Register (Address 0x00 P1.5 P1.4 P1.3 R/W R/W R Figure 6-9. Port 1 Data Register (Address 0x01) CY7C63001A CY7C63101A b2 b1 T.2 T 1.024-ms interrupt 128- s interrupt Resonator Clock Timer Register b2 b1 P0.2 P0.1 R/W R/W ...

  • Page 9

    ... GPIO interrupt “0” selects a HIGH to LOW transition while a “1” selects a LOW to HIGH transition PULL0.4 PULL0 Figure 6-11. Port 0 Pull-up Register (Address 0x08) CY7C63001A CY7C63101A GPIO Pin Interrupt Polarity High to Low Low to High High to Low Hi-Z Low to High b2 b1 PULL0 ...

  • Page 10

    ... Figure 6-15 illustrates the format of the Global Interrupt Enable Register EP1IE EP0IE R/W R generates an interrupt request enabled in the Global Interrupt Enable Register. The highest priority interrupt request is serviced following the execution of the current instruction. CY7C63001A CY7C63101A b2 b1 PULL1.2 PULL1 ISINK2 ISINK1 W W ...

  • Page 11

    ... CLR D Q Enable [1] CLK CLR D Q Enable [6] CLK CLR D Q Enable [7] CLK CY7C63001A CY7C63101A Function Reset 128- s timer interrupt 1.024-ms timer interrupt USB endpoint 0 interrupt USB endpoint 1 interrupt Reserved GPIO interrupt Wake-up interrupt 128-ms CLR 128-ms IRQ 1-ms CLR 1-ms IRQ ...

  • Page 12

    ... USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process. When a GPIO interrupt is serviced, the ISR must poll the ports to determine which pin caused the interrupt. CY7C63001A CY7C63101A b2 b1 IE0.2 IE0 ...

  • Page 13

    ... Configuration and Report descriptors. 10.The USB Controller retrieves the descriptors from its program space and returns the data to the host over the USB. 11.Enumeration is complete after the host has received all the descriptors. CY7C63001A CY7C63101A USB Engine USB Enumeration Process b2 b1 ...

  • Page 14

    ... Valid Yes OUT Error Yes OUT Valid No OUT Error No OUT Valid No OUT Error No OUT Status No OUT N/Status No OUT Error No CY7C63001A CY7C63101A OUT R/W R Section The ‘StatusOuts’ USB Engine Response Toggle Count Update Update Interrupt Yes Yes Yes Yes Yes ...

  • Page 15

    ... Endpoint 0. A valid Status stage OUT contains a DATA1 packet with 0 bytes of data. If the Statu- sOuts bit is set, the USB engine responds to a valid Status stage OUT with an ACK, and any other OUT with a STALL. CY7C63001A CY7C63101A b2 b1 ...

  • Page 16

    ... In addition to the differ- ential receiver, there is a single-ended receiver for each of the two data lines. The single-ended receivers have a switching threshold between 0.8V and 2.0V (TTL inputs). CY7C63001A CY7C63101A Low-Speed Driver Characteristics Signal pins pass output ...

  • Page 17

    ... CEXT XTALIN XTALOUT ± 7.5kW 0.1 F 6-MHz Resonator Port0 Port0 Switches, Devices, Etc. Port1 Port1 D– CEXT CC XTALIN XTALOUT 0.1 F 6-MHz Resonator CY7C63001A CY7C63101A 2.6 2.8 3.0 3.2 1% +4.35V (min) 4.7 F +3.3V 3.3V Reg 0.1 F ± 1.5 kW +4.35V (min.) 4.7 F Page ...

  • Page 18

    ... XOR [expr], XOR [X+expr], IOWX [X+expr CPL 1B 6 ASL 1C 4 ASR 1D 5 RLC 1E 13 RRC 1F 4 RET JNC Ax 5 JACC Bx 5 INDEX CY7C63001A CY7C63101A operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address 29 5 address 2A 5 ...

  • Page 19

    ... Vout = 2.0V DC, Port 0 only Vout = 2.0V DC, Port 1 only Vout = 2.0V DC, Port 1 only Vout = 0.4V DC, Port 1 only Vout = 2.0V DC, Port Port 0 or Port 1 [12] Vout = 2.0V Full scale transition Summed over all Port 1 bits . CC CY7C63001A CY7C63101A [1] ................................................ > 200 mA = 4.0 to 5.25V CC Min. Max. [2] –0.4 256 7.168 8 ...

  • Page 20

    ... See Note 5 Ave. Bit Rate (1.5 Mb/s ± 1.5%) [10] To Next Transition, Figure 9-3 For Paired Transitions, Figure 9-3 [10] [10] Accepts as EOP To next transition, Figure 9-5 To paired transition, Figure 9-5 CY7C63001A CY7C63101A = 4.0 to 5.25V (continued) CC Min. Max. Unit 25 mW 45% 65% V ...

  • Page 21

    ... T JR Consecutive Transitions PERIOD JR1 Paired Transitions PERIOD JR2 Figure 9-3. Receiver Jitter Tolerance Crossover Point Extended Crossover Point Diff. Data to SE0 Skew PERIOD DEOP CY7C63001A CY7C63101A t f 90% 10 JR1 JR2 Source EOP Width: T EOPT Receiver EOP Width EOPR1 EOPR2 Page ...

  • Page 22

    ... T PERIOD Differential Data Lines 10.0 Ordering Information EPROM Ordering Code Size CY7C63001A-PC 4KB CY7C63001A-PXC 4KB CY7C63001A-SC 4KB CY7C63001A-SXC 4KB CY7C63101A-QC 4KB CY7C63101A-QXC 4KB CY7C63001A-XC 4KB CY7C63001A-XWC 4KB 11.0 Package Diagrams Document #: 38-08026 Rev. *A Crossover Points Consecutive Transitions PERIOD xJR1 Paired Transitions ...

  • Page 23

    ... Package Diagrams (continued) Document #: 38-08026 Rev. *A 24-Lead Quarter Size Outline Q13 20-Lead (300-Mil) Molded SOIC S5 CY7C63001A CY7C63101A 51-85055-*B 51-85024-*B Page ...

  • Page 24

    ... Table 11-1 below shows the die pad coordinates for the CY7C63001A-XC and CY7C63001A-XWC. The center location of each bond pad is relative to the bottom left corner of the die which has coordinate (0,0). Table 11-1. CY7C63001A-XC Probe Pad Coordinates in Microns ((0,0) to Bond Pad Centers) Pin X Pad # ...

  • Page 25

    ... Document History Page Document Title: CY7C63001A, CY7C63101A Universal Serial Bus Microcontroller Document Number: 38-08026 REV. ECN NO. Issue Date ** 116223 06/12/02 *A 276070 See ECN Document #: 38-08026 Rev. *A Orig. of Change Description of Change DSG Change from Spec number: 38-00662 to 38-08026 BON Added die form and bond pad information. Added lead-free packages. ...