MPC8241LVR200D Freescale Semiconductor, MPC8241LVR200D Datasheet - Page 22

• Manufacturer Part Number: MPC8241LVR200D
• Description: IC MPU 32BIT 200MHZ PPC 357-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerPCr

Specifications of MPC8241LVR200D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xxx
• Core: 603e
• Maximum Clock Frequency: 200 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 357
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: 0°C To +105°C
• Family Name: MPC82XX
• Device Core: PowerQUICC II
• Device Core Size: 32b
• Frequency (max): 200MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical and Thermal Characteristics
22
Shown in 2:1 Mode
SDRAM_SYNC_IN
Notes:
VM = Midpoint voltage (1.4 V).
10b-d = Input signals valid timing.
11a = Input hold time of SDRAM_SYNC_IN to memory.
12b-d = sys_logic_clk to output valid timing.
13b = Output hold time for non-PCI signals.
14b = SDRAM-SYNC_IN to output high-impedance timing for non-PCI signals.
T
PCI_SYNC_IN
os
Inputs/Outputs
(after DLL locks)
PCI_SYNC_IN
Inputs/Outputs
= Offset timing required to align sys_logic_clk with SDRAM_SYNC_IN. The SDRAM_SYNC_IN signal
sys_logic_clk
is adjusted by the DLL to accommodate for internal delay. This causes SDRAM_SYNC_IN to appear
before sys_logic_clk once the DLL locks.
Figure 11. Input/Output Timing Diagram Referenced to SDRAM_SYNC_IN
Memory
Figure 12. Input/Output Timing Diagram Referenced to PCI_SYNC_IN
PCI
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
10a
10b-d
Input Timing
T
Input Timing
GV
os
VM
DD
0.4 x
VM
VM
_OV
GV
DD
DD
2
_OV
11a
11c
2.0 V
0.8 V
DD
GV
2.0 V
0.8 V
12a
DD
VM
12b-d
2
_OV
DD
Output Timing
GV
Output Timing
DD
0.615
0.285
_OV
14a
13a
DD
14b
13b
x
GV
Freescale Semiconductor
DD
VM
_OV
2
DD