MPC8241LVR200D Freescale Semiconductor, MPC8241LVR200D Datasheet - Page 30

• Manufacturer Part Number: MPC8241LVR200D
• Description: IC MPU 32BIT 200MHZ PPC 357-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerPCr

Specifications of MPC8241LVR200D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 200MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC8xxx
• Core: 603e
• Maximum Clock Frequency: 200 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 200MHz
• Digital Ic Case Style: BGA
• No. Of Pins: 357
• Supply Voltage Range: 1.14V To 1.26V
• Operating Temperature Range: 0°C To +105°C
• Family Name: MPC82XX
• Device Core: PowerQUICC II
• Device Core Size: 32b
• Frequency (max): 200MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical and Thermal Characteristics
Figure 20
30
Notes:
1. TRST is an asynchronous signal. The setup time is for test purposes only.
2. Nontest (other than TDI and TMS) signal input timing with respect to TCK.
3. Nontest (other than TDO) signal output timing with respect to TCK.
Num
11
12
13
TMS, TDI data hold time
TCK to TDO data valid
TCK to TDO high impedance
through
Data Outputs
Data Outputs
TRST
Data Inputs
Table 15. JTAG AC Timing Specification (Independent of PCI_SYNC_IN)
TCK
TCK
Figure 23
TCK
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
3
Figure 22. JTAG Boundary Scan Timing Diagram
show the different timing diagrams for JTAG.
Figure 20. JTAG Clock Input Timing Diagram
Characteristic
Figure 21. JTAG TRST Timing Diagram
VM = Midpoint Voltage
3
5
VM
8
9
2
4
1
Input Data Valid
VM
6
Output Data Valid
Min
15
0
0
2
7
VM
Max
15
15
—
Freescale Semiconductor
Unit
ns
ns
ns
Notes
—
—
—