A80386DX16 Intel, A80386DX16 Datasheet - Page 78

• Manufacturer Part Number: A80386DX16
• Description: IC MPU 32-BIT 5V 16MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX16

• Processor Type: 386DX
• Features: 32-bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 16MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807050

Intel386
When address pipelining is not used the address
and bus cycle definition remain valid during all wait
states When wait states are added and you desire
to maintain non-pipelined address timing it is neces-
sary to negate NA
last one as shown in Figure 5-12 cycles 2 and 3 If
NA
last one the next state would be T2I (for pipelined
address) or T2P (for pipelined address) instead of
another T2 (for non-pipelined address)
When address pipelining is not used the bus states
and transitions are completely illustrated by Figure
5-13 The bus transitions between four possible
states T1 T2 Ti and Th Bus cycles consist of T1
and T2 with T2 being repeated for wait states Oth-
erwise the bus may be idle in the Ti state or in hold
acknowledge the Th state
When address pipelining is not used the bus state
diagram is as shown in Figure 5-13 When the bus is
78
Bus States
T1 first clock of a non-pipelined bus cycle (Intel386 DX drives new address and asserts ADS )
T2 subsequent clocks of a bus cycle when NA
Ti
Th hold acknowledge state (Intel386 DX asserts HLDA)
The fastest bus cycle consists of two states T1 and T2
Four basic bus states describe bus operation when not using pipelined address These states do include BS16
bus size If asserting BS16
idle state
is sampled asserted during a T2 other than the
TM
DX MICROPROCESSOR
Figure 5-13 Intel386
during each T2 state except the
requires a second 16-bit bus cycle to be performed it is performed before HOLD asserted is acknowledged
has not been sampled asserted in the current bus cycle
TM
DX Bus States (not using pipelined address)
idle it is in state Ti Bus cycles always begin with T1
T1 always leads to T2 If a bus cycle is not acknowl-
edged during T2 and NA
ed When a cycle is acknowledged during T2 the
following state will be T1 of the next bus cycle if a
bus request is pending internally or Ti if there is no
bus request pending or Th if the HOLD input is be-
ing asserted
The bus state diagram in Figure 5-13 also applies to
the use of BS16
adjustments for 16-bit bus size the adjustments do
not affect the external bus states If an additional
16-bit bus cycle is required to complete a transfer on
a 16-bit bus it also follows the state transitions
shown in Figure 5-13
Use of pipelined address allows the Intel386 DX to
enter three additional bus states not shown in Figure
5-13 Figure 5-20 in 5 4 3 4 Pipelined Address is
the complete bus state diagram including pipelined
address cycles
If the Intel386 DX makes internal
is negated T2 is repeat-
usage for 32-bit and 16-bit
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