A80386DX16 Intel, A80386DX16 Datasheet - Page 87

• Manufacturer Part Number: A80386DX16
• Description: IC MPU 32-BIT 5V 16MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX16

• Processor Type: 386DX
• Features: 32-bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 16MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807050

Certain types of 16-bit or 8-bit operands require no
adjustment for correct transfer on a 16-bit bus
Those are read or write operands using only the low-
er half of the data bus and write operands using
only the upper half of the bus since the Intel386 DX
simultaneously duplicates the write data on the low-
er half of the data bus For these patterns of Byte
Enables and the R W
asserted at the Intel386 DX allowing NA
serted during the bus cycle if desired
5 4 4 Interrupt Acknowledge (INTA)
In response to an interrupt request on the INTR in-
put when interrupts are enabled the Intel386 DX
Interrupt Vector (0– 255) is read on D0– D7 at end of second Interrupt Acknowledge bus cycle
Because each Interrupt Acknowledge bus cycle is followed by idle bus states asserting NA
which is simplest for your system hardware design
Cycles
signals BS16
Figure 5-22 Interrupt Acknowledge Cycles
need not be
to be as-
performs two interrupt acknowledge cycles These
bus cycles are similar to read cycles in that bus defi-
nition signals define the type of bus activity taking
place and each cycle continues until acknowledged
by READY
The state of A2 distinguishes the first and second
interrupt acknowledge cycles The byte address
driven during the first interrupt acknowledge cycle is
4 (A31 – A3 low A2 high BE3 – BE1
BE0
interrupt acknowledge cycle is 0 (A31 – A2 low
BE3 – BE1
low) The address driven during the second
Intel386
sampled asserted
high BE0
has no practical effect Choose the approach
TM
DX MICROPROCESSOR
low)
231630 –26
high and
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