MC68EC030FE25C Freescale Semiconductor, MC68EC030FE25C Datasheet - Page 27

• Manufacturer Part Number: MC68EC030FE25C
• Description: IC MPU 32 BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

M O T O R O L A
N O T E S :
10. These specifications allow system designers to guarantee that an alternate bus master has stopped
11.
12. These hold times are specified with respect to strobes (asynchronous) and with respect to the clock
13. Synchronous inputs must meet specifications #60 and #61 with stable logic levels for all rising edges of
14. This specification allows system designers to qualify the
1. This number can be reduced to 5 ns if strobes have equal loads.
2. If the asynchronous setup time (#47A) requirements are satisfied, the
3. This parameter specifies the maximum allowable skew between
4. This specification applies to the first (
5.
6. The minimum values must be met to guarantee proper operation. If this maximum value is exceeded,
7. This specification indicates the minimum high time for
8. This specification guarantees operation with the MC68881/MC68882, which specifies a minimum time
9. This specification allows a system designer to guarantee data hold times on the output side of data
DS
DBEN
(#31) and
data-in clock low setup time (#27) for the following clock cycle and
BERR
DSACK1
DSACKx
BG
followed immediately by another cache hit, a cache miss, or an operand cycle.
for
Without this specification, incorrect interpretation of specifications #9A and #15 would indicate that
the MC68EC030 does not meet the MC68881/MC68882 requirements.
buffers that have output enable signals generated with
for synchronous READ cycles with no wait states.
driving the bus when the MC68EC030 regains control of the bus after an arbitration sequence.
(synchronous). The designer is free to use either time.
the clock while
edge. The values originally published were specified relative to the low level of the rising clock edge.
(allowing 7 ns for a gate delay) and still meet the
MC68881/MC68882 User's Manual) .
will not be asserted for synchronous write cycles with no wait states.
may be reasserted.
DS
may stay asserted on consecutive write cycles.
low to clock low setup time (#27A) for the following clock cycle.
negated to
,
to
DSACKx
BERR
DSACK0
AS
is an asynchronous input using the asynchronous input setup time (#47A).
is asserted. These values are specified relative to the high level of the rising clock
low to
AS
asserted; specification #47A must be met by
Freescale Semiconductor, Inc.
asserted (specification #13A in the MC68881/MC68882 User's Manual ).
BERR
For More Information On This Product,
MC68EC030 TECHNICAL DATA
low setup time (#48) can be ignored. The data must only satisfy the
DSACK0
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or
DSACK1
CS
ECS
to
DBEN
DS
and
CS
)
DSACKx
signal of an MC68881/MC68882 with
setup time requirement (spec 8B of the
OCS
. The timing on
in the event of an internal cache hit
DSACK0
DSACK0
signal asserted. In the absence of
BERR
DSACKx
must only satisfy the late
or
to
DBEN
DSACK1
low to data setup time
DSACK1
precludes its use
.
asserted or
AS
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