Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 106

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Refresh Register 2
RFEN (Refresh Enable). Enables the refresh function when
programmed to logic 1.
Reserved bit 6. Read as 0, should write to as 0.
BS5-BS0 (Burst Size). This field defines the number of
refresh transactions per refresh request made to the Z380
MPU's External Interface Logic. The burst size ranges from
1 to 64, with the highest size specified with BS5-BS0 equal
to 0s.
7
RFSHR2: 00000015H
R/W
RFEN
0
--
0
Figure 49. Refresh Register 2
BS5
0
BS4
0
BS3
0
BS2 BS1 BS0
0
0
0
0
<- Reset Value
Burst Size
Reserved
Refresh Enable
Refresh Wait Register
T1W2-T1W0 (T1 Waits). This binary field defines up to
seven T1 wait states to be inserted in refresh transactions.
T1W1-T2W0 (T2 Waits). This binary field defines up to
three T2 wait states to be inserted in refresh transactions.
T3W2-T3W0 (T3 Waits). This binary field defines up to
seven T3 wait states to be inserted in refresh transactions.
Note that care should be exercised in defining refresh
burst size and request intervals to avoid over-burdening
the system bus with refresh transactions. The memory chip
select signals can be selectively enabled to go active
during refresh transactions, such enabling is described in
the Memory Chip Selects and Waits section.
7
RFWR: 0000000FH
R/W
T1W2
1
T1W1 T1W0 T2W1 T2W0 T3W2 T3W1 T3W0
1
Figure 50. Refresh Waits Register
1
1
1
1
1
Page 106 of 125
1
0
<- Reset Value
T3 Waits
T2 Waits
T1 Waits