Z8038018FSG Zilog, Z8038018FSG Datasheet - Page 34

• Manufacturer Part Number: Z8038018FSG
• Description: IC 16 BIT Z80 MPU 100-QFP
• Manufacturer: Zilog

Specifications of Z8038018FSG

• Processor Type: Z380
• Features: 16-Bit, High-Performance Enhanced Z80 CPU
• Speed: 18MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z80380x
• Core: Z380
• Program Memory Size: 64 KB
• Maximum Clock Frequency: 18 MHz
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDRESS
PS010002-0708
/INTAK
/IOWR
IOCLK
/IORQ
/IORD
/WAIT
DATA
/M1
1
The RETI transaction is ten IOCLK cycles long unless extended by Wait states, and
/WAIT is sampled at three separate points during the transaction. /WAIT is first sampled in
the middle of the third IOCLK cycle to allow for longer/IORDLow-time requirements.
/WAIT is then sampled again during the middle of the fifth IOCLK cycle to allow for lon-
ger internal daisy-chain settling time within the peripheral. Wait states inserted here have
the effect of separating what the peripheral sees as two separate instruction fetch cycles.
Finally, /WAIT is sampled in the middle of the ninth IOCLK cycle, again to allow for lon-
ger /IORD Low-time requirements.
The Z380 MPU drives the data bus throughout the RETI transaction, with EDEDH during
the first half of the transaction (the first byte of a RETI instruction is EDH) and with
4D4DH during the second half of the transaction (the second byte of an RETI instruction
is 4DH).
2
Figure 23. Return From Interrupt Cycle
EDED
3
4
5
6
7
4D4D
Z380 Microprocessor
Product Specification
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