MC68020EH16E Freescale Semiconductor, MC68020EH16E Datasheet - Page 117

• Manufacturer Part Number: MC68020EH16E
• Description: IC MPU 32BIT 33MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020EH16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.7.2 MC68EC020 Bus Arbitration
The sequence of the MC68EC020 bus arbitration protocol is as follows:
BR may be issued any time during a bus cycle or between cycles. BG is asserted in
response to B R; it is usually asserted as soon as BR has been synchronized and
recognized, except when the MC68020 has made an internal decision to execute a bus
cycle. Then, the assertion of BG is deferred until the bus cycle has begun. Additionally, BG
is not asserted until the end of a read-modify-write operation (when RMC is negated) in
response to a BR signal. When the requesting device receives BG and more than one
external device can be bus master, the requesting device should begin whatever
arbitration is required. The external device continues to assert BR when it assumes bus
mastership, and maintains BR during the entire bus cycle (or cycles) for which it is bus
master. The following conditions must be met for an external device to assume mastership
of the bus through the normal bus arbitration procedure:
Figure 5-46 is a flowchart of MC68EC020 bus arbitration for a single device. Figure 5-47 is
a timing diagram for the same operation. This technique allows processing of bus
requests during data transfer cycles.
Bus arbitration requests are recognized during normal processing, RESET assertion,
HALT assertion, and when the processor has halted due to a double bus fault.
5-70
1. An external device asserts the BR signal.
2. The processor asserts the BG signal to indicate that the bus will become available at
3. The external device asserts the BR signal throughout its bus mastership.
• The external device must have received BG through the arbitration process.
• AS must be negated, indicating that no bus cycle is in progress, and the external
• The termination signal (DSACK1/DSACK0) for the most recent cycle must have been
• No other bus master has claimed ownership of the bus.
device must ensure that all appropriate processor signals have been placed in the
high-impedance state (by observing specification #7 in Section 10 Electrical
Specifications).
negated, indicating that external devices are off the bus.
the end of the current bus cycle.
Freescale Semiconductor, Inc.
For More Information On This Product,
M68020 USER’S MANUAL
Go to: www.freescale.com
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