MC68020EH16E Freescale Semiconductor, MC68020EH16E Datasheet - Page 136

• Manufacturer Part Number: MC68020EH16E
• Description: IC MPU 32BIT 33MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020EH16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
6.1.9 Interrupt Exceptions
When a peripheral device requires the services of the MC68020/EC020 or is ready to
send information that the processor requires, it may signal the processor to take an
interrupt exception. The interrupt exception transfers control to a routine that responds
appropriately.
The peripheral device uses the IPL2 – IPL0 signals to signal an interrupt condition to the
processor and to specify the priority of that condition. These three signals encode a value
of zero through seven ( IPL0 is the least significant bit). When IPL2 – IPL0 are all negated,
the interrupt request level is zero. IPL2 – IPL0 values 1–7 specify one of seven levels of
prioritized interrupts; level 7 has the highest priority. External circuitry can chain or
otherwise merge signals from devices at each level, allowing an unlimited number of
devices to interrupt the processor.
The IPL2 – I P L 0 signals must maintain the interrupt request level until the
MC68020/EC020 acknowledges the interrupt to guarantee that the interrupt is recognized.
The MC68020/EC020 continuously samples the IPL2 – IPL0 signals on consecutive falling
edges of the processor clock to synchronize and debounce these signals. An interrupt
request that is the same for two consecutive falling clock edges is considered a valid
input. Although the protocol requires that the request remain until the processor runs an
interrupt acknowledge cycle for that interrupt value, an interrupt request that is held for as
short a period as two clock cycles could be recognized.
The I2–I0 bits in the SR specify the interrupt priority mask. The value in the interrupt mask
is the highest priority level that the processor ignores. When an interrupt request has a
priority higher than the value in the mask, the processor makes the request a pending
interrupt. Figure 6-2 is a flowchart of the procedure for making an interrupt pending.
When several devices are connected to the same interrupt level, each device should hold
its interrupt priority level constant until its corresponding interrupt acknowledge cycle to
ensure that all requests are processed.
Table 6-3 lists the interrupt levels, the states of IPL2 – IPL0 that define each level, and the
mask value that allows an interrupt at each level.
MOTOROLA
M68020 USER’S MANUAL
6- 11
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