MC68020EH16E Freescale Semiconductor, MC68020EH16E Datasheet - Page 71

• Manufacturer Part Number: MC68020EH16E
• Description: IC MPU 32BIT 33MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020EH16E

• Processor Type: M680x0 32-Bit
• Speed: 166MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16.67MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
5.2.6 Bus Operation
The MC68020/EC020 bus is used in an asynchronous manner allowing external devices
to operate at clock frequencies different from the MC68020/EC020 clock. Bus operation
uses the handshake lines (AS, DS, DSACK0, DSACK1, BERR, and HALT) to control data
transfers. AS signals the start of a bus cycle, and DS is used as a condition for valid data
on a write cycle. Decoding SIZ1, SIZ0, A1, and A0 provides byte enable signals that select
the active portion of the data bus. The slave device (memory or peripheral) then responds
by placing the requested data on the correct portion of the data bus for a read cycle or
latching the data on a write cycle and by asserting the DSACK0/DSACK1 combination that
corresponds to the port size to terminate the cycle. If no slave responds or the access is
invalid, external control logic asserts BERR to abort or BERR and HALT to retry the bus
cycle.
DSACK1/DSACK0 can be asserted before the data from a slave device is valid on a read
cycle. The length of time that DSACK1/DSACK0 may precede data is given by parameter
#31, and it must be met in any asynchronous system to ensure that valid data is latched
into the processor. (Refer to Section 10 Electrical Characteristics for timing
parameters.) Note that no maximum time is specified from the assertion of AS to the
assertion of DSACK1/DSACK0. Although the processor can transfer data in a minimum of
three clock cycles when the cycle is terminated with DSACK1/DSACK0, the processor
inserts wait cycles in clock period increments until DSACK1/DSACK0 is recognized.
The BERR and/or HALT signals can be asserted after DSACK1/ DSACK0 is asserted.
BERR and/or HALT must be asserted within the time given (parameter #48), after
DSACK1/DSACK0 is asserted in any asynchronous system. If this maximum delay time is
violated, the processor may exhibit erratic behavior.
DSACK1
DSACK0
5.2.7 Synchronous Operation with
/
Although cycles terminated with DSACK1/DSACK0 are classified as asynchronous, cycles
terminated with DSACK1/DSACK0 can also operate synchronously in that signals are
interpreted relative to clock edges. The devices that use these synchronous cycles must
synchronize the responses to the MC68020/EC020 clock. Since these devices terminate
bus cycles with D S A C K 1/D S A C K 0 , the dynamic bus sizing capabilities of the
MC68020/EC020 are available. In addition, the minimum cycle time for these synchronous
cycles is three clocks.
To support systems that use the system clock to generate DSACK1/DSACK0 and other
asynchronous inputs, the asynchronous input setup time (parameter #47A) and the
asynchronous input hold time (parameter #47B) are provided in Section 10 Electrical
Characteristics. (Note: although a misnomer, these “asynchronous” parameters are the
setup and hold times for synchronous operation.) If the setup and hold times are met for
the assertion or negation of a signal, such as DSACK1/DSACK0, the processor can be
guaranteed to recognize that signal level on that specific falling edge of the system clock.
If the assertion of DSACK1/DSACK0 is recognized on a particular falling edge of the clock,
valid data is latched into the processor (for a read cycle) on the next falling clock edge
provided the data meets the data setup time (parameter #27). In this case, parameter #31
5-24
M68020 USER’S MANUAL
MOTOROLA
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