MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 153

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

6-16
input signal (CIIN) when the data in a long word is not cachable. If the
tinue driving the address and bus control signals and to latch a new data
two cache entries within a cache line, the first cycle corresponds to the cache
the second, third, and fourth cycles are run in burst mode. A distinction is
The bus controller requests a burst mode fill operation by asserting the cache
with STERM, it should not acknowledge the request with the assertion of the
The cache burst request signal (CBREQ) requests burst mode operation from
the referenced external device. To operate in the burst mode, the device or
value for the next cache entry at the completion of each subsequent cycle
When a cacne burst is initiated, the first cycle attempts to load the cache
entry corresponding to the instruction word or data item explicitly requested
entry containing the portion of the operand at the lower address.
cycles are requested by the bus controller. Therefore, when data from the
first cycle is returned, it is immediately available for the execution unit (EU).
first cycle is complete. The microsequencer must wait for the burst operation
to complete before requesting the second portion of the operand. Normally,
the request for the second portion results in a data cache hit unless the second
one to four long words of cachable data, or it may assert the cache inhibit
cache burst acknowledge (CBACK) signal. The MC68030 ignores the assertion
of CBACK during cycles terminated with DSACKx.
external hardware must be able to increment the low-order address bits if
required, and the current cycle must be a 32-bit synchronous transfer (STERM
must be asserted) as described in SECTION 7 BUS OPERATION. The device
must also assert CBACK (at the same time as STERM) at the end of the cycle
in which the MC68030 asserts CBREQ. CBACK causes the processor to con-
(as defined by STERM), for a total of up to four cycles (until four long words
have been read).
by the execution unit. The subsequent cycles are for the subsequent entries
in the cache line. In the case ofa misaligned transfer when the operand spans
Figure 6-11 illustrates the four cycles of a burst operation and shows that
made between the first cycle of a burst operation and the subsequent cycles
because the first cycle is requested by the microsequencer and the burst fill
However, data from the burst fill cycles is not available to the EU until the
burst operation is complete. Since the microsequencer makes two separate
operand returned during a burst operation is available to the EU after the
cycle of the burst operation terminates abnormally.
burst request signal (CBREQ). The responding device may sequentially supply
responding device does not support the burst mode and it terminates cycles
requests for misaligned data operands, only the first portion of the misaligned
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