MC68030FE20C Freescale Semiconductor, MC68030FE20C Datasheet - Page 188

• Manufacturer Part Number: MC68030FE20C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
7.2.8 Asynchronous Operation
The BERF~ and/or HALT signals can be asserted after the DSACKx signal(s)
ferent from the clock for the MC68030. Asynchronous operation requires
to control data transfers. Using this method, AS signals the start of a bus
the size outputs and lower address lines (A0 and A1) provides strobes that
to terminate the cycle. If no slave responds or the access is invalid, external
the bus cycle, respectively.
The DSACKx signals can be asserted before the data from a slave device is
valid on a read cycle. The length of time that DSACKx may precede data is
MC68030 Electrical Specifications for timing parameters.) Notice that no max-
Although the processor can transfer data in a minimum of three clock cycles
when the cycle is terminated with DSACKx, the processor inserts wait cycles
parameter #48, after DSACKx is asserted in any asynchronous system. If this
maximum delay time is violated, the processor may exhibit erratic behavior.
where the first portion of the operand results in a cache hit (but the bus
The MC68030 bus may be used in an asynchonous manner. In that case, the
external devices connected to the bus can operate at clock frequencies dif-
cycle, and DS is used as a condition for valid data on a write cycle. Decoding
select the active portion of the data bus. The slave device (memory or pe-
of the data bus for a read cycle or latching the data on a write cycle, and
asserting the DSACKt/DSACK0 combination that corresponds to the port size
control logic asserts the BERR or BERR and HALT signal(s) to abort or retry
given by parameter #31, and it must be met in any asynchronous system to
insure that valid data is latched into the processor. (Refer to MC68030EC/D,
imum time is specified from the assertion of AS to the assertion of DSACKx.
in clock period increments until DSACKx is recognized.
is asserted. BERR and/or HALT must be asserted within the time given as
controller is executing other cycles, these aborted cycles due to cache hits
of an operand transfer. Therefore, in the case of a misaligned data transfer
controller did not begin an external cycle and then abort it) and the second
portion in a cache miss, OCS is asserted for the second portion ofthe operand.
using only the handshake line (AS, DS, DSACK1, DSACK0, BERR, and HALT)
ripheral) then responds by placing the requested data on the correct portion
is hitting in both caches and if the bus controller is free. Note that, if the bus
may not be seen externally. Also, OCS is asserted for the first external cycle
MC68030 USER'S
MANUAL
7-27