MC68EC040FE25A Freescale Semiconductor, MC68EC040FE25A Datasheet
MC68EC040FE25A
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... Freescale Semiconductor, Inc. MOTOROLA M68360QUADS-040 User’s Manual ISSUE 1.0 - DRAFT For More Information On This Product, Go to: www.freescale.com Thi d t MICROPROCESSOR & MEMORY TECHNOLOGIES GROUP t d ith SIX SIGMA 6 MOTOROLA ...
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... Freescale Semiconductor, Inc GENERAL INFORMATION 1.1 INTRODUCTION 1.2 RELATED DOCUMENTATION 1.3 ABBREVIATIONS USED IN THE DOCUMENT 1.4 SPECIFICATIONS 1.5 COOLING REQUIREMENTS 1.6 FEATURES 1.7 HARDWARE BLOCK DIAGRAM 2 - Hardware Preparation and Installation 2.1 INTRODUCTION 2.2 UNPACKING INSTRUCTIONS 2.3 HARDWARE PREPARATION 2.3.1 ADI Port Address Selection 2 ...
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... Freescale Semiconductor, Inc. 3.4 Programming the slave QUICC 3.4.1 Module Base Address Register 3.4.2 Module Configuration Register 3.4.3 CLKO Control Register 3.4.4 PLL Control Register 3.4.5 Port E Pin Assignment Register 3.4.6 System Protection Control 3.4.7 Global Memory Register 3.4.8 Base Register 0 and Option Register 0 3 ...
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... Freescale Semiconductor, Inc. 4.11.2 Chip Select TA~ and DSACK~ Generator 4.11.3 ADI Port 4.11.3.1 4.11.4 RS-232 Serial Port 4.11.4.1 4.11.5 M68360QUADS-040 Status Register 4.11.5.1 4.11.6 Ethernet Controller 4.11.6.1 4.11.6.2 4.11.7 Serial EEPROM 4.11.8 Slave QUICC General Purpose I/O Pins 4.11.8.1 4.11.8.2 4.11.8.3 4 ...
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... Freescale Semiconductor, Inc. FIGURE 2-1 M68360QUADS Location diagram FIGURE 2-2 Configuration Dip-Switch - DSW1 FIGURE 2-3 P6: +5V Power Connector FIGURE 2-4 P6: +12V Power Connector FIGURE 2 ADI Port Connector FIGURE 2 RS-232 Serial Port Connector FIGURE 4-1 Arbitration Scheme: FIGURE 4-2 ADI Port Connector ...
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... Freescale Semiconductor, Inc. TABLE 1-1. M68360QUADS-040 Specifications TABLE 3-1. EC040 Cycle Types and Responding Devices TABLE 3-2 M68360QUADS-040 Main Memory Map TABLE 4-1. DRAM SIMM Types TABLE 4-2 Port A Pins Description TABLE 4-3 Port B Pins Description TABLE 4-4 Port C Pins Description ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 1 - GENERAL INFORMATION 1.1 INTRODUCTION This document describes the evaluation board for the MC68EC040 - MC68360 combination called the M68360QUADS-040. This board is constructed with an MC68EC040 as the master processor and a MC68360 (QUICC slave in MC68EC040 companion mode. The purpose of this board is to evaluate the performance of the above combination, rather than serve as a development system ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual TABLE 1-1. M68360QUADS-040 Specifications CHARACTERISTICS Addressing Total address range: on-board - Off-board - Flash Memory Dynamic RAM EEPROM Operating temperature Storage temperature Relative humidity Dimensions: Height Depth Thickness a. The 12V supply is not used on the board connected only to the Ethernet AUI connectors P3 & supplied to the network. Therefore, the power consumption of that supply is independent of the M68360QUADS-040 MHz components are used to get better s.u. timing between the QUICC & ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 1.6 FEATURES Following are the main features of the M68360QUADS-040: Master MC68EC040FE33 with 32-bit address bus, 32 bit data bus, instruction and data caches. Supports also MC68LC040. 1 Mbyte Dynamic RAM, 60 nsec access time, 36 bits wide (data and parity) SIMM, accessed with 3,2,2,2 clock cycles ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 5. Dual-port Ethernet controller. VMEbus double-height board dimensions SOFT-RESET, HARD-RESET and ABORT switches. Status LEDs for power, EC040 run, DMA run, HALT and Ethernet signals. Single +5Vdc power supply. 1.7 HARDWARE BLOCK DIAGRAM Logic Analyzer Connectors ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 2 - Hardware Preparation and Installation 2.1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation, and installation instructions for the M68360QUADS-040. 2.2 UNPACKING INSTRUCTIONS If the shipping carton is damaged upon receipt, request unpacking and inspection of equipment. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual FIGURE 2-1 M68360QUADS Location diagram For More Information On This Product, Go to: www.freescale.com Hardware Preparation and Installation SOFT RESET SW1 SW2 ABORT 12 ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 2.3.1 ADI Port Address Selection The M68360QUADS-040 can have eight possible slave addresses set for its ADI port, enabling up to eight M68360QUADS-040 boards to be connected to the same ADI board in the host computer. The selection of the slave address is done by setting switches 6, 7 & ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 2.3.2 Caches Enable / Disable Switch #1 on DSW1 enables / disables the MC68EC040 caches. When ’OFF’ position (FACTORY SETUP) both caches may be enabled by software. When ’ON’ position, both instruction and data caches can not be enabled by software. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 2.4.1 +5V Power Supply Connection The M68360QUADS-040 requires +5 Vdc @ 5 A max, power supply for operation. Connect the +5V power supply to connector P11 as shown below: FIGURE 2-3 P6: +5V Power Connector VCC Gnd Gnd terminal block power connector with power plug. The plug is designed to accept AWG wires ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual FIGURE 2 ADI Port Connector (+ 12 v) N.C. HOST_VCC HOST_VCC HOST_VCC HOST_ENABLE~ NOTE: Pin 26 on the ADI is connected to +12 v power supply, but it is not used in the M68360QUADS-040. 2.4.5 Terminal to M68360QUADS-040 RS-232 Connection In the stand-alone operation mode, a VT100 compatible terminal should be connected to the RS-232 connector P2 ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 3 - OPERATING INSTRUCTIONS 3.1 INTRODUCTION This chapter provides necessary information to use the M68360QUADS-040 in host-controlled and stand- alone configurations. This includes controls and indicators, memory map details, and software initialization of the board. 3.2 CONTROLS AND INDICATORS The M68360QUADS-040 has the following switches and indicators ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual When the TPSQEL (Twisted Pair Signal Quality Error Test Enable) jumper - position, the collision detect circuitry test is enabled, i.e., simulated collision is generated to the EEST collision detect circuitry. The generated collision does not have any effect over the TP media. When J4 is removed, the above test is disabled ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 3.2.11 DMARUN Indicator - LD9 The yellow DMARUN indicator is connected to AS* signal of the slave QUICC, this to indicate bus activity of one of the QUICC’s DMA channels. 3.2.12 Ethernet TX Indicator - LD3 The green LED Ethernet Transmit indicator blinks whenever the EEST is transmitting data through one of the Ethernet ports ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual TABLE 3-1. EC040 Cycle Types and Responding Devices TM(2:0) TT(1:0) Address Space 100 00 MMU Table b Search Code 101 0X Supervisor Data 110 00 Supervisor Program 111 00 Supervisor CPU 111 11 Supervisor CPU a. For 68LC040 only, reserved otherwise b ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 3.4 Programming the slave QUICC The slave QUICC (core disabled) provides the following functions on the M68360QUADS-040: 1. DRAM Controller 2. Chip Select and DSACK~ generator. 3. Parallel port (ADI). 4. UART for terminal or host computer connection. 5. Dual Ethernet controller. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual bus fault monitor and to enable the bus monitor function to respond after 1 K clock cycles in the slave QUICC. 3.4.7 Global Memory Register The global memory register (GMR) contains selections for the memory controller of the slave QUICC. The ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual • For MCM36256 or MCM36512 types: • For 100 nsec access time - 3FF00001 • For 80 nsec or 70 nsec access time - 2FF00001 • For 60 nsec access time 1FF00001 • For MCM36100 or MCM36200 types: • For 100 nsec access time - 3FC00001 • ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 3.4.13 Base Register 5 and Option Register 5 Base register 5 (BR5) and Option register 5 (OR5) control the operation of CS5~ pin of the slave QUICC, which is connected to the Status Register and to the level -7 interrupt logic. When CS5~ is asserted (for read-only) both the Status Register is read and all existing level - 7 status bits are cleared. BR5 must be initialized to ’ ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 3.4.22 Port B Data Direction Register The port B data direction register (PBDIR) has different functions according to the configuration of the port pins pin is general purpose I/O pin, the value in the PBDIR for that pin defines the direction of the pin. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 4 - FUNCTIONAL DESCRIPTION 4.1 INTRODUCTION This chapter details the hardware design of the M68360QUADS-040, and describes each module in order to simplify the design. 4.2 Master MC68EC040 The CPU on the M68360QUADS-040 MHz MC68EC040, running at 25 MHz, which uses the slave QUICC’ ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 4.2.2 Utilizing the MC68EC040 Data Cache In order to achieve best performance out of the MC68EC040, both caches, Instruction and Data, are used. Since the bus interface of the EC040 and the QUICC’s DMA are different, snooping is not supported on the M68360QUADS-040 ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual push-button - SW1, HARD - reset is generated to board. Indication for the occurrence of that interrupt is concluded from the absence of both Host NMI and Hardware-Breakpoint indications in the status register. 4.3.2 Host - NMI When a host is connected to the M68360QUADS-040 via the ADI port possible for the host to generate a level - 7 interrupt via the ADI port, allowing for full interrupt, the host computer needs to assert and deassert the ADS_BRK signal of the ADI port ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual FIGURE 4-1 Arbitration Scheme: Since the level of priority associated with the BR~ input is lower (8) than the SDMA’s, no use is done with the BCLRO~ signal of the QUICC is not used. In sake of simplicity, no use is done with the IPEND~ is not used as a BCLI~ for the QUICC ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 4.5.3 Spurious Interrupt Monitor In EC040 mode, the QUICC monitors for spurious interrupt cycles performed by the EC040. This support is limited to those levels supported internally by the QUICC interrupter, i.e., only on those levels used by the CPM and the SIM60. If such a condition occurs, the QUICC terminates the cycle with TEA~. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual Additional BSRAM components should be soldered with care. Otherwise permanent damage may be inflicted to the M68360QUADS-040. The bursting sram may be accessed by both the EC040 and the DMA, however access by the QUICC must be EVEN WORD aligned. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 4.11.1 DRAM Controller The slave QUICC device provides the necessary control signals for the DRAM module. The debugger on the M68360QUADS-040 reads the presence detect pins (SIMM1 - SIMM4) of the SIMM found in the status register and sets the DRAM Controller parameters according to the DRAM module’s size and access time. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual The ADI port connector pin, male, D type connector. The connection between the M68360QUADS- 040 and the host computer line flat cable, supplied with the ADI board. FIGURE 4-2 below shows the pin configuration of the connector. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual • ADS_SEL(0:2) - ’I’ These three input lines determine the slave address of the M68360QUADS-040 being accessed by the host computer boards can be addressed by one ADI board. • ADS_ALL - ’I’ This input line is used to reset or abort program execution on all M68360QUADS-040 development boards that are connected to the same ADI board. • ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual The RS-232 serial port connector pin, male, D-type connector as shown in FIGURE 2-6. FIGURE 4-3 RS-232 Serial Port Connector 4.11.4.1 RS-232 Port Signal Description In the list below, the directions ’I’, ’O’, and ’I/O’ are relative to the M68360QUADS-040 board. (I.E. ’I’ means input to the M68360QUADS-040) • ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual • SIMM4 to SIMM1 - These four bits, encode the data identifying the DRAM SIMM connected to the M68360QUADS-040. For the various DRAM types supported, refer to TABLE 4-1. • BKINT* - When active ’0’, indicates that the last level 7 interrupt (NMI) was generated by the Hardware Breakpoint logic. • ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual • +12V ( +12V power supply from the M68360QUADS-040. 4.11.6.2 Ethernet Twisted-Pair Port Signal Description The twisted-pair port connector pin, RJ-45 connector as shown in FIGURE 2-6. FIGURE 4-6 Ethernet Twisted-Pair Port Connector The list below describes the port signals. The directions ’I’, ’O’, and ’I/O’ are relative to the M68360QUADS- 040 board. (I.E. ’ ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual Port pins port. TABLE 4-2 describes the configuration of port A. TABLE 4-2 Port A Pins Description Pin Pin Name Description 0 EEST RX This pin is connected to the receive data output of the EEST configured as the receive data of SCC1 in the slave QUICC. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual Port pins port. TABLE 4-2 describes the configuration of port B. TABLE 4-3 Port B Pins Description Pin Pin Name Description 0 EEPROM This pin is connected to the select input of the EEPROM, and it is configured as Select output pin in the slave QUICC. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual Port pins port. TABLE 4-2 describes the configuration of port C. TABLE 4-4 Port C Pins Description Pin Pin Name Description 0 EEST TENA This pin is connected to the TENA input of the EEST configured as the RTS signal of SCC1 in the slave QUICC. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 5 - SUPPORT INFORMATION 5.1 INTRODUCTION This chapter provides the interconnection signals, parts list, and schematic diagrams of the M68360QUADS-040 board. 5.2 INTERCONNECT SIGNALS The M68360QUADS-040 board interconnects with external devices through the following connectors: • ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual TABLE 5-1 Connector P1 Interconnect Signals Pin No. Signal Name Description 15 - Not connected 16 PD1 Bit 1 of the ADI port data bus 17 PD3 Bit 3 of the ADI port data bus 18 PD5 Bit 5 of the ADI port data bus ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual TABLE 5-3 Connector P3 Interconnect Signals Pin No. Signal Name Description 2 ACX+ Collision detect positive input to the M68360QUADS-040. 3 ATX+ Transmit Data positive output from the M68360QUADS-040. 4 GND Ground signal of the M68360QUADS-040. 5 ARX+ Receive Data positive input to the M68360QUADS-040. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual TABLE 5-5 Connector P5 Interconnect Signals Pin No. Signal Name Description 5 ARX+ Receive Data positive input to the M68360QUADS-040. 6 GND Ground signal of the M68360QUADS-040 Not connected 8 GND Ground signal of the M68360QUADS-040. 9 ACX- Collision detect negative input to the M68360QUADS-040. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual TABLE 5-8 Connector P8 Interconnect Signals Pin No. Signal Name Description C4 TT0 Transfer Type signal 0 pin of the EC040 C5 GND M68360QUADS-040 board Ground SIZ0 - SIZ1 EC040’s Access Size indicators BRQ~ Quicc’s Bus Request C9 BGQ~ Quicc’ ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual TABLE 5-9 Connector P9 Interconnect Signals Pin No. Signal Name Description A4 SIA_TX SIA Transmit Data. Also SCC2’s Transmit Data GND Board’s GND PA6 - PA7 Port Parallel I/O lines A9 GND Board’s Ground A10 CLKO1 Quicc’ ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual TABLE 5-9 Connector P9 Interconnect Signals Pin No. Signal Name Description C17 MI~ EC040’s Memory Inhibit output C18 CIOUT~ EC040 Cache Inhibit Out C19 IPEND~ EC040 Interrupt Pending output C20 CDIS~ EC040’s Cache Disable input ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual Reference Designation C16, C17 Capacitor 100 pF C20 Capacitor 0.039 F C29 Capacitor 3900 pF C32, C33 Capacitor 68 pF C50 Capacitor 390 pF D1 MBRD620CT D2 1SMC5.0AT3 (zener) DSW1 DIP-SWITCH, SPST 8 F1 Fuse Block, with 5A fuse J10 ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual Reference Designation R24 Resistor 100 R25 - R28 Resistor 150 RN1 RN2 Resistor network 16 pin, 8 resistors 22 RN3 - RN10 Resistor network 14 pin, 13 resistors 4.7 K SW1, SW2 S.P.D.T. push button T1, T3 I.C. PE64503 T2 I.C. PE65263 T4 I.C. PE65260 U1 ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual . For More Information On This Product, Go to: www.freescale.com SUPPORT INFORMATION 50 ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual APPENDIX A - ADI BOARD INSTALLATION A.1 INTRODUCTION This appendix describes the hardware installation of the ADI board into various host computers. The installation instructions cover the following host computers: 1. IBM-PC/XT/AT 2. SUN - 4 (SBus interface) A.2 IBM-PC/XT/AT to M68360QUADS-040 Interface The ADI board should be installed in one of the IBM-PC/XT/AT motherboard system expansion slots ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual FIGURE A-1 Physical Location of jumper JG1 and JG2 JG1 JG2 NOTE: Jumper JG2 should be left unconnected. The following figure shows the required jumper connection for each address configuration. Address 0 hex is not recommended, and its usage might cause problems. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual BEFORE REMOVING OR INSTALLING ANY EQUIPMENT IN THE SUN-4 COMPUTER, TURN THE POWER OFF AND REMOVE THE POWER CORD. A.3.1 ADI Installation in the SUN-4 There are no jumper options on the ADI board for the Sun-4 computer. The ADI board can be inserted into any available SBus expansion slot on the motherboard ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 5. Push the ADI board against the back panel and align the connector with its mate and gently press the corners of the board to seat the connector firmly. 6. Close the system unit. 7. Connect the 37 pin interface flat cable to the ADI board and secure. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual APPENDIX B - ADI PORT HANDSHAKE DESCRIPTION B.1 INTRODUCTION In this appendix, the ADI port signals and the handshake procedure are explained. The M68360QUADS- 040 ADI port can be connected to an ADI board mounted in a host computer. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual FIGURE B-1 Host Computer (ADI) to M68360QUADS-040 Connection HOST COMPUTER B.3.1 Write Cycle from Host to M68360QUADS-040 The application software in the Host uses the handshake signals to coordinate data transfer across the parallel link. The QUICC040bug software in the M68360QUADS-040 is responsible for accepting the data and responding to the handshake signals ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual 6. The Host detects the ADS_ACK signal and negates the HOST_REQ signal (data buffer is disabled). 7. The M68360QUADS-040 detects the negation of HOST_REQ signal and negates ADS_ACK to end the cycle. FIGURE B-2 Host Write to M68360QUADS-040 1 ADS_SEL(0:2) ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual FIGURE B-3 M68360QUADS-040 Write Cycle to Host 1 ADS_REQ PD(0:7) ADS_SEL(0:2) HST_ACK B.3.3 M68360QUADS-040 Interrupt to the Host The M68360QUADS-040 can generate an interrupt to the Host. The interrupt request and acknowledge sequence is shown in FIGURE B-4. The sequence is as follows: 1 ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual FIGURE B-4 M68360QUADS-040 Interrupt to Host HOST_BRK~ 1 ADS_INT PD(0:7) 2 ADS_SEL(0:2) 3 HST_ACK INT_ACK B.3.4 Host Interrupt to the M68360QUADS-040 The Host can interrupt the M68360QUADS-040 (interrupt level 7) to abort the execution of programs running on the board. This is done by selecting the address of the required M68360QUADS-040 and momentarily asserting the ADS_BRK signal, which sets a latch in the M68360QUADS-040 ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual APPENDIX C - PALS’ EQUATIONS C.1 U10 - Indicators Logic TITLE INDICATR PATTERN INDICATR.PDS REVISION PILOT.0 DATE 8,8,93 ;******************************************************** CHIP INDIC PAL20RA10 ;*************************** PL PST0 PST1 PST2 PST3 TIP AS ADSNT BKCLR CK_NMI CS5 GND ; H_BRK H_BRK_ H_NMI HLT RUNDM RUN040 VCC ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual /HLT = VCC HLT.TRST = /PST3 * PST2 * /PST1 * PST0 HLT.RSTF = VCC; bypass HLT.SETF = VCC H_NMI.CLKF = CK_NMI ; rising edge of CK_NMI /H_NMI := VCC H_NMI.TRST = VCC H_NMI.RSTF = /CS5 H_NMI.SETF = GND H_BRK_ = GND H_BRK_.TRST = H_BRK H_BRK_.RSTF = VCC ; bypass H_BRK_.SETF = VCC H_BRK.CLKF = /ADSNT ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual ; BKINT serves holding the request from the breakpoint logic. ; RSTS_ is a simulated o.c. driving the soft reset line of the quicc, while ; its OE is driven by RSTS ; RSTH_ is a simulated o.c. driving the hard reset line of the quicc, while ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual ABRT.CLKF = DEB2 ; rising edge of abort debouncer. /ABRT := VCC ; active low. ABRT.TRST = VCC ABRT.RSTF = /CS5 ; reset the FF ('1') ABRT.SETF = GND RSTS = H_RSTS ; host generated SOFT reset + DEB1 * /DEB2 ; SOFT reset push button depressed + /RSTO ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual RSTH_.TRST = RSTH RSTH_.RSTF = VCC ; bypass RSTH_.SETF = VCC C.3 U12 - ADI Controller ; Reference Designation - U3 Title PARALLEL_CONT Pattern PARCONT.pds Revision A.0 Date 23,12,92 ;******************************************************** CHIP PARCONT PAL22V10 ;*************************** ADS_G RSTS HSVCC ADRST ADALL ADBRK HSTEN HSACK HSREQ INACK NC GND ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual H_RSTH = HSTEN * /HSVCC * /ADRST * ADSSEL * /INACK + HSTEN * /HSVCC * /ADRST * /ADALL * /INACK CK_NMI = HSTEN * /HSVCC * /ADBRK * ADSSEL + HSTEN * /HSVCC * /ADBRK * /ADALL /BKCLR = /RSTS + /INACK * HSTEN * /HSVCC * ADSSEL /ADI_RD = HSTEN * ADSSEL * /HSVCC /ADI_G = HSTEN * /HSVCC * ADSSEL * /HSACK; host reads + HSTEN * /HSVCC * ADSSEL * /ADS_G ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual ; S_RST: Synchronized RESETH ; DS_RST: Double synchronized RESETH ; D_RST: Detect RESETH asserted. ; CONF2: QUICC CONFIG2 pin, which determines core disable Q5: counter stages ; RESETH: QUICCs hard reset i/o pin - active low. ; CIN: Active high count enable. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual Q1.TRST = VCC /Q1 * D_RST * CIN + Q2 * /Q0 * D_RST * CIN + / D_RST * CIN + Q2 * D_RST * /CIN Q2.TRST = VCC /Q2 * D_RST * CIN + Q3 * /Q1 * D_RST * CIN + Q3 * /Q0 * D_RST * CIN + / D_RST * CIN + Q3 * D_RST * /CIN Q3.TRST = VCC /Q3 * D_RST * CIN + Q4 * /Q2 * D_RST * CIN + Q4 * /Q1 * D_RST * CIN ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual GLOBAL.SETF = GND GLOBAL.RSTF = GND C.5 U32 - Bursting Sram Controller Title SRAMCONT Pattern SRAMCNT.pds Revision PILOT.0 Date 15,8,93 ;******************************************************** CHIP SRAMCNT PAL16R4 ;******************************************************************* ; This pal serves as a bursting sram controller, for the QUICC040EVB. ; SRMG(1:2) are active-low G (oe) for the sram banks. ...
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... Freescale Semiconductor, Inc. M68360QUADS-040 Hardware User’s Manual /BAA1 := SIZ1 * SIZ0 * /TSC * /CS3 * R_W * TA * /TIP ; burst read + SIZ1 * SIZ0 * TSC * /CS3 * /R_W * /TA * /TIP + /BAA1 * /CS3 /BAA2 := SIZ1 * SIZ0 * /TSC * /CS4 * R_W * TA * /TIP ; burst read + SIZ1 * SIZ0 * TSC * /CS4 * /R_W * /TA * /TIP + /BAA2 * /CS4 /SAS := /AS CS4.TRST = GND ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...