MPC8347EVVALFB Freescale Semiconductor, MPC8347EVVALFB Datasheet - Page 92

• Manufacturer Part Number: MPC8347EVVALFB
• Description: IC MPU POWERQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347EVVALFB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 667MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3V
• Operating Supply Voltage (max): 1.36V
• Operating Supply Voltage (min): 1.24V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Design Information
21.3
Due to large address and data buses and high operating frequencies, the MPC8347E can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8347E system, and the
MPC8347E itself requires a clean, tightly regulated source of power. Therefore, the system designer
should place at least one decoupling capacitor at each V
MPC8347E. These capacitors should receive their power from separate V
GND power planes in the PCB, with short traces to minimize inductance. Capacitors can be placed directly
under the device using a standard escape pattern. Others can surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, distribute several bulk storage capacitors around the PCB, feeding the V
and LV
have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also
be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors are 100–330 µF (AVX TPS tantalum or Sanyo OSCON).
21.4
To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low
inputs should be tied to OV
connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
the MPC8347E.
21.5
The MPC8347E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I
To measure Z
or GND. Then the value of each resistor is varied until the pad voltage is OV
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R
OV
other in value. Then, Z
92
DD
/2. R
DD
Connection Recommendations
Decoupling Recommendations
Output Buffer DC Impedance
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should
P
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
then becomes the resistance of the pull-up devices. R
0
for the single-ended drivers, an external resistor is connected from the chip pad to OV
0
= (R
DD
P
, GV
+ R
N
DD
)/2.
, or LV
DD
as required. Unused active high inputs should be
2
DD
C).
P
, OV
is trimmed until the voltage at the pad equals
DD
DD
, GV
P
and R
, GV
DD
DD
, LV
N
DD
are designed to be close to each
, and LV
DD
, OV
DD
, OV
/2 (see
DD
DD
DD
Freescale Semiconductor
, GV
DD
pin of the
, and GND pins of
Figure
, OV
DD
, LV
DD
43). The
, GV
DD
, and
DD
DD
,