MC68020CRC25E Freescale Semiconductor, MC68020CRC25E Datasheet - Page 118

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MC68020CRC25E

Manufacturer Part Number
MC68020CRC25E
Description
IC MICROPROCESSOR 32BIT 114-PGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68020CRC25E

Processor Type
M680x0 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
114-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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5.7.2.1 BUS REQUEST (MC68EC020). External devices capable of becoming bus
masters request the bus by asserting BR. BR can be a wire-ORed signal (although it need
not be constructed from open-collector devices) that indicates to the processor that some
external device requires control of the bus. The processor is at a lower bus priority level
than the external device and relinquishes the bus after it has completed the current bus
cycle (if one has started). BR remains asserted throughout the external device’s bus
mastership.
5.7.2.2 BUS GRANT (MC68EC020). The processor asserts BG as soon as possible after
receipt of the bus request. BG assertion immediately follows internal synchronization
except during a read-modify-write cycle or follows an internal decision to execute a bus
cycle. During a read-modify-write cycle, the processor does not assert BG until the entire
operation has completed. RMC is asserted to indicate that the bus is locked. In the case of
an internal decision to execute another bus cycle, BG is deferred until the bus cycle has
begun.
BG may be routed through a daisy-chained network or through a specific priority-encoded
network. The processor allows any type of external arbitration that follows the protocol.
MOTOROLA
Figure 5-46. MC68EC020 Bus Arbitration Flowchart for Single Request
1) ASSERT BG
RE-ARBITRATE OR RESUME
PROCESSOR OPERATION
GRANT BUS ARBITRATION
PROCESSOR
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
M68020 USER’S MANUAL
1) ASSERT BR
1) NEGATE BR
1) EXTERNAL ARBITRATION DETERMINES
2) NEXT BUS MASTER WAITS FOR
3) PERFORM DATA TRANSFERS
NEXT BUS MASTER
CURRENT CYCLE TO COMPLETE
(READ AND WRITE CYCLES)
ACKNOWLEDGE BUS MASTERSHIP
RELEASE BUS MASTERSHIP
OPERATE AS BUS MASTER
REQUESTING DEVICE
REQUEST THE BUS
5- 71

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