MC68020CRC25E Freescale Semiconductor, MC68020CRC25E Datasheet - Page 85

• Manufacturer Part Number: MC68020CRC25E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020CRC25E

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

State 0
State 1
State 2
State 3
5-38
MC68020—The write cycle starts in S0. The processor negates ECS, indicating the
MC68EC020—The write cycle starts in S0. During S0, the processor places a valid
MC68020—One-half clock later in S1, the processor asserts AS, indicating that the
MC68EC020—One-half clock later in S1, the processor asserts AS, indicating that the
MC68020/EC020—During S2, the processor places the data to be written onto D31–D0.
MC68020/EC020—The processor asserts DS during S3, indicating that the data on the
beginning of an external cycle. If the cycle is the first external cycle of a write
operation, OCS is asserted simultaneously. During S0, the processor places a valid
address on A31–A0 and valid function codes on FC2–FC0. The function codes select
the address space for the cycle. The processor drives R/W low for a write cycle. SIZ1–
SIZ0 become valid, indicating the number of bytes to be transferred.
address on A23–A0 and valid function codes on FC2–FC0. The function codes select
the address space for the cycle. The processor drives R/W low for a write cycle. SIZ1,
SIZ0 become valid, indicating the number of bytes to be transferred.
address on the address bus is valid. The processor also asserts DBEN during S1,
which can enable external data buffers. In addition, the ECS (and OCS, if asserted)
signal is negated during S1.
address on the address bus is valid.
At the end of S2, the processor samples DSACK1/DSACK0.
data bus is stable. As long as at least one of the DSACK1/DSACK0 signals is
recognized by the end of S2 (meeting the asynchronous input setup time requirement),
the cycle terminates one clock later. If DSACK1/DSACK0 is not recognized by the start
of S3, the processor inserts wait states instead of proceeding to S4 and S5. To ensure
that wait states are inserted, both DSACK1 and DSACK0 must remain negated
throughout the asynchronous input setup and hold times around the end of S2. If wait
states are added, the processor continues to sample the DSACK1/DSACK0 signals on
the falling edges of the clock until one is recognized.
The external device uses R/W , DS, SIZ1, SIZ0, A1, and A0 to latch data from the
appropriate byte(s) of the data bus (D31–D24, D23–D16, D15–D8, and D7–D0). SIZ1,
SIZ0, A1, and A0 select the bytes of the data bus. If it has not already done so, the
device asserts DSACK1/DSACK0 to signal that it has successfully stored the data.
Freescale Semiconductor, Inc.
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M68020 USER’S MANUAL
Go to: www.freescale.com
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