MC68020CRC25E Freescale Semiconductor, MC68020CRC25E Datasheet - Page 210

• Manufacturer Part Number: MC68020CRC25E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020CRC25E

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor, Inc.
The protocol used to execute coprocessor cpSAVE, cpRESTORE, or conditional category
instructions does not change when a trace exception is pending in the main processor.
The main processor performs a pending trace on instruction execution exception after
completing the execution of that instruction. If the main processor is in the trace on
change of flow mode and an instruction places an address other than that of the next
instruction in the PC, the processor takes a trace exception after it executes the
instruction.
If a trace exception is not pending during a general category instruction, the main
processor terminates communication with the coprocessor after reading any primitive with
CA = 0. Thus, the coprocessor can complete a cpGEN instruction concurrently with the
execution of instructions by the main processor. When a trace exception is pending,
however, the main processor must ensure that all processing associated with a cpGEN
instruction has been completed before it takes the trace exception. In this case, the main
processor continues to read the response CIR and to service the primitives until it receives
either a null primitive with CA = 0 and PF = 1 or until exception processing caused by a
take postinstruction exception primitive has completed. The coprocessor should return the
null primitive with CA = 0 and PF = 0 while it is completing the execution of the cpGEN
instruction. The main processor may service pending interrupts between reads of the
response CIR if IA = 1 in these primitives (refer to Table 7-3). This protocol ensures that a
trace exception is not taken until all processing associated with a cpGEN instruction has
completed.
If T1, T0 = 01 in the MC68020/EC020 SR (trace on change of flow mode) when a general
category instruction is initiated, a trace exception is taken for the instruction only when the
coprocessor issues a transfer status register and scanPC primitive with DR = 1 during the
execution of that instruction. In this case, it is possible that the coprocessor is still
executing the cpGEN instruction concurrently when the main processor begins execution
of the trace exception handler. A cpSAVE instruction executed during the trace on change
of flow exception handler could thus suspend the execution of a concurrently operating
cpGEN instruction.
7.5.2.6 INTERRUPTS. Interrupt processing, discussed in Section 6 Exception
Processing, can occur at any instruction boundary. Interrupts are also serviced during the
execution of a general or conditional category instruction under either of two conditions. If
the main processor reads a null primitive with CA = 1 and IA = 1, it services any pending
interrupts prior to reading the response CIR. Similarly, if a trace exception is pending
during cpGEN instruction execution and the main processor reads a null primitive with CA
= 0, IA = 1, and PF = 0 (refer to 7.5.2.5 Trace Exceptions), the main processor services
pending interrupts prior to reading the response CIR again.
The MC68020/EC020 uses the 10-word midinstruction stack frame (see Figure 7-43)
when it services interrupts during the execution of a general or conditional category
coprocessor instruction. Since it uses this stack frame, the main processor can perform all
necessary processing and then return to read the response CIR. Thus, it can continue
execution of the coprocessor instruction during which the interrupt exception occurred.
MOTOROLA
M68020 USER’S MANUAL
7- 57
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