A80386DX33 Intel, A80386DX33 Datasheet - Page 110

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

Intel386
6 2 INSTRUCTION ENCODING
6 2 1 Overview
All instruction encodings are subsets of the general
instruction format shown in Figure 6-1 Instructions
consist of one or two primary opcode bytes possibly
an address specifier consisting of the ‘‘mod r m’’
byte and ‘‘scaled index’’ byte a displacement if re-
quired and an immediate data field if required
Within the primary opcode or opcodes smaller en-
coding fields may be defined These fields vary ac-
cording to the class of operation The fields define
such information as direction of the operation size
of the displacements register encoding or sign ex-
tension
Almost all instructions referring to an operand in
memory have an addressing mode byte following
the primary opcode byte(s) This byte the mod r m
byte specifies the address mode to be used Certain
Note Table 6-1 shows encoding of individual instructions
110
Field Name
w
d
s
reg
mod r m
ss
index
base
sreg2
sreg3
tttn
7
T T T T T T T T T T T T T T T T mod T T T r m
(one or two bytes)
TM
(T represents an
opcode bit )
DX MICROPROCESSOR
opcode
0 7
Specifies if Data is Byte or Full Size (Full Size is either 16 or 32 Bits
Specifies Direction of Data Operation
Specifies if an Immediate Data Field Must be Sign-Extended
General Register Specifier
Address Mode Specifier (Effective Address can be a General Register)
Scale Factor for Scaled Index Address Mode
General Register to be used as Index Register
General Register to be used as Base Register
Segment Register Specifier for CS SS DS ES
Segment Register Specifier for CS SS DS ES FS GS
For Conditional Instructions Specifies a Condition Asserted
or a Condition Negated
Table 6-2 Fields within Intel386
0
Figure 6-1 General Instruction Format
7 6 5 3 2 0
‘‘mod r m’’
byte
register and address
mode specifier
Description
ss index base d32
7 6 5 3 2 0
‘‘s-i-b’’
encodings of the mod r m byte indicate a second
addressing byte the scale-index-base byte follows
the mod r m byte to fully specify the addressing
mode
Addressing modes can include a displacement im-
mediately following the mod r m byte or scaled in-
dex byte If a displacement is present the possible
sizes are 8 16 or 32 bits
If the instruction specifies an immediate operand
the immediate operand follows any displacement
bytes The immediate operand if specified is always
the last field of the instruction
Figure 6-1 illustrates several of the fields that can
appear in an instruction such as the mod field and
the r m field but the Figure does not show all fields
Several smaller fields also appear in certain instruc-
tions sometimes within the opcode bytes them-
selves Table 6-2 is a complete list of all fields ap-
pearing in the Intel386 DX instruction set Further
ahead following Table 6-2 are detailed tables for
each field
byte
TM
DX Instructions
displacement
(4 2 1 bytes
l
or none)
address
16
l
8
l
none data32
(4 2 1 bytes
Number of Bits
immediate
or none)
l
2 for mod
data
16
3 for r m
l
1
1
1
3
2
3
3
2
3
4
8
l
none