A80386DX33 Intel, A80386DX33 Datasheet - Page 65

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

Intel386 DX I O cycles are automatically generated
for coprocessor communication Since the Intel386
DX must transfer 32-bit quantities between itself and
the Intel387 DX BS16
ing Intel387 DX communication cycles
5 2 7 Bus Arbitration Signals
5 2 7 1 INTRODUCTION
This section describes the mechanism by which the
processor relinquishes control of its local buses
when requested by another bus master device See
5 5 1 Entering and Exiting Hold Acknowledge for
additional information
5 2 7 2 BUS HOLD REQUEST (HOLD)
This input indicates some device other than the In-
tel386 DX requires bus mastership
HOLD must remain asserted as long as any other
device is a local bus master HOLD is not recognized
while RESET is asserted If RESET is asserted while
HOLD is asserted RESET has priority and places
the bus into an idle state rather than the hold ac-
knowledge (high impedance) state
HOLD is level-sensitive and is a synchronous input
HOLD signals must always meet setup and hold
times t
5 2 7 3 BUS HOLD ACKNOWLEDGE (HLDA)
Assertion of this output indicates the Intel386 DX
has relinquished control of its local bus in response
to HOLD asserted and is in the bus Hold Acknowl-
edge state
The Hold Acknowledge state offers near-complete
signal isolation In the Hold Acknowledge state
HLDA is the only signal being driven by the Intel386
DX The other output signals or bidirectional signals
(D0–D31 BE0 – BE3
M IO
ance state so the requesting bus master may control
them Pullup resistors may be desired on several sig-
nals to avoid spurious activity when no bus master is
driving them See 7 2 3 Resistor Recommenda-
tions Also one rising edge occuring on the NMI
input during Hold Acknowledge is remembered for
processing after the HOLD input is negated
In addition to the normal usage of Hold Acknowl-
edge with DMA controllers or master peripherals
23
(HOLD HLDA)
LOCK
and t
24
for correct operation
and ADS ) are in a high-imped-
must not be asserted dur-
A2– A31 W R
D C
the near-complete isolation has particular attractive-
ness during system test when test equipment drives
the system and in hardware-fault-tolerant applica-
tions
5 2 8 Coprocessor Interface Signals
5 2 8 1 INTRODUCTION
In the following sections are descriptions of signals
dedicated to the numeric coprocessor interface In
addition to the data bus address bus and bus cycle
definition signals these following signals control
communication between the Intel386 DX and its In-
tel387 DX processor extension
5 2 8 2 COPROCESSOR REQUEST (PEREQ)
When asserted this input signal indicates a coproc-
essor request for a data operand to be transferred
to from memory by the Intel386 DX In response
the Intel386 DX transfers information between the
coprocessor and memory Because the Intel386 DX
has internally stored the coprocessor opcode being
executed it performs the requested data transfer
with the correct direction and memory address
PEREQ is level-sensitive and is allowed to be asyn-
chronous to the CLK2 signal
5 2 8 3 COPROCESSOR BUSY (BUSY )
When asserted this input indicates the coprocessor
is still executing an instruction and is not yet able to
accept another When the Intel386 DX encounters
any coprocessor instruction which operates on the
numeric stack (e g load pop or arithmetic opera-
tion) or the WAIT instruction this input is first auto-
matically sampled until it is seen to be negated This
sampling of the BUSY
the execution of a previous coprocessor instruction
The FNINIT and FNCLEX coprocessor instructions
are allowed to execute even if BUSY
since these instructions are used for coprocessor
initialization and exception-clearing
BUSY
chronous to the CLK2 signal
BUSY
sampled LOW at the falling edge of RESET the In-
tel386 DX performs an internal self-test (see 5 5 3
Bus Activity During and Following Reset) If
BUSY
(PEREQ BUSY
is level-sensitive and is allowed to be asyn-
is sampled HIGH no self-test is performed
serves an additional function If BUSY
Intel386
TM
DX MICROPROCESSOR
input prevents overrunning
ERROR )
is asserted
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is