A80386DX33 Intel, A80386DX33 Datasheet - Page 50

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

Intel386
4 4 5 Call Gates
Gates provide protected indirect CALLs One of the
major uses of gates is to provide a secure method of
privilege transfers within a task Since the operating
system defines all of the gates in a system it can
ensure that all gates only allow entry into a few trust-
ed procedures (such as those which allocate memo-
ry or perform I O)
Gate descriptors follow the data access rules of priv-
ilege that is gates can be accessed by a task if the
EPL is equal to or more privileged than the gate
descriptor’s DPL Gates follow the control transfer
rules of privilege and therefore may only transfer
control to a more privileged level
Call Gates are accessed via a CALL instruction and
are syntactically identical to calling a normal subrou-
tine When an inter-level Intel386 DX call gate is ac-
tivated the following actions occur
The procedure is identical for 80286 Call gates ex-
cept that 16-bit parameters are copied and 16-bit
registers are pushed
Interrupt Gates and Trap gates work in a similar
fashion as the call gates except there is no copying
of parameters The only difference between Trap
and Interrupt gates is that control transfers through
an Interrupt gate disable further interrupts (i e the IF
bit is set to 0) and Trap gates leave the interrupt
status unchanged
4 4 6 Task Switching
A very important attribute of any multi-tasking multi-
user operating systems is its ability to rapidly switch
between tasks or processes The Intel386 DX direct-
ly supports this operation by providing a task switch
instruction in hardware The Intel386 DX task switch
operation saves the entire state of the machine
50
I O Ports Accessible 2
1 Load CS EIP from gate check for validity
2 SS is pushed zero-extended to 32 bits
3 ESP is pushed
4 Copy Word Count 32-bit parameters from the
5 Push Return address on stack
old stack to the new stack
TM
DX MICROPROCESSOR
9 12 13 15 20
Figure 4-15b Sample I O Permission Bit Map
24 27 33 34 40 41 48 50 52 53 58
(all of the registers address space and a link to the
previous task) loads a new execution state per-
forms protection checks and commences execution
in the new task in about 17 microseconds Like
transfer of control via gates the task switch opera-
tion is invoked by executing an inter-segment JMP
or CALL instruction which refers to a Task State
Segment (TSS) or a task gate descriptor in the GDT
or LDT An INT n instruction exception trap or ex-
ternal interrupt may also invoke the task switch op-
eration if there is a task gate descriptor in the asso-
ciated IDT descriptor slot
The TSS descriptor points to a segment (see Figure
4-15) containing the entire Intel386 DX execution
state while a task gate descriptor contains a TSS
selector The Intel386 DX supports both 80286 and
Intel386 DX style TSSs Figure 4-16 shows a 80286
TSS The limit of an Intel386 DX TSS must be great-
er than 0064H (002BH for a 80286 TSS) and can be
as large as 4 Gigabytes In the additional TSS
space the operating system is free to store addition-
al information such as the reason the task is inac-
tive time the task has spent running and open files
belong to the task
Each task must have a TSS associated with it The
current TSS is identified by a special register in the
Intel386 DX called the Task State Segment Register
(TR) This register contains a selector referring to
the task state segment descriptor that defines the
current TSS A hidden base and limit register associ-
ated with TR are loaded whenever TR is loaded with
a new selector Returning from a task is accom-
plished by the IRET instruction When IRET is exe-
cuted control is returned to the task which was in-
terrupted The current executing task’s state is
saved in the TSS and the old task state is restored
from its TSS
Several bits in the flag register and machine status
word (CR0) give information about the state of a
task which are useful to the operating system The
Nested Task (NT) (bit 14 in EFLAGS) controls the
function of the IRET instruction If NT
instruction performs the regular return when NT
1 IRET performs a task switch operation back to the
previous task The NT bit is set or reset in the follow-
ing fashion
60 62 63 96
127
e
231630 –71
0 the IRET
e