A80386DX33 Intel, A80386DX33 Datasheet - Page 67

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

5 2 10 Signal Summary
Table 5-4 summarizes the characteristics of all Intel386 DX signals
5 3 BUS TRANSFER MECHANISM
5 3 1 Introduction
All data transfers occur as a result of one or more
bus cycles Logical data operands of byte word and
double-word lengths may be transferred without re-
strictions on physical address alignment Any byte
boundary may be used although two or even three
physical bus cycles are performed as required for
unaligned operand transfers See 5 3 4 Dynamic
Data Bus Sizing and 5 3 6 Operand Alignment
CLK2
D0–D31
BE0 –BE3
A2 –A31
W R
D C
M IO
LOCK
ADS
NA
BS16
READY
HOLD
HLDA
PEREQ
BUSY
ERROR
INTR
NMI
RESET
Signal Name
Clock
Data Bus
Byte Enables
Address Bus
Write-Read Indication
Data-Control Indication
Memory-I O Indication
Bus Lock Indication
Address Status
Next Address Request
Bus Size 16
Transfer Acknowledge
Bus Hold Request
Bus Hold Acknowledge
Coprocessor Request
Coprocessor Busy
Coprocessor Error
Maskable Interrupt Request
Non-Maskable Intrpt Request
Reset
Signal Function
Table 5-4 Intel386
TM
Active
State
High
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
DX Signal Summary
The Intel386 DX address signals are designed to
simplify external system hardware Higher-order ad-
dress bits are provided by A2 – A31 Lower-order ad-
dress in the form of BE0 – BE3
linear selects for the four bytes of the 32-bit data
bus Physical operand size information is thereby im-
plicitly provided each bus cycle in the most usable
form
Byte Enable outputs BE0 – BE3
when their associated data bus bytes are involved
with the present bus cycle as listed in Table 5-5
During a bus cycle any possible pattern of contigu-
ous asserted Byte Enable outputs can occur but
never patterns having a negated Byte Enable sepa-
rating two or three asserted Enables
Output
Input
I O
O
O
O
O
O
O
O
O
Intel386
I
I
I
I
I
I
I
I
I
I
I
Synch or
to CLK2
Asynch
TM
Input
A
A
A
A
A
S
S
S
S
S
S
DX MICROPROCESSOR
High Impedance
During HLDA
directly provides
Output
are asserted
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
67