MC68306FC16B Freescale Semiconductor, MC68306FC16B Datasheet - Page 39

• Manufacturer Part Number: MC68306FC16B
• Description: IC MPU INTEGRATED 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68306FC16B

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The descriptions of the eight states of a write cycle are as follows:
STATE 0
STATE 1
STATE 2
STATE 3
STATE 4
STATE 5
STATE 6
STATE 7
STATE 5
STATE 6
STATE 7
STATE 8
STATE 9
3.1.3 Read-Modify-Write Cycle
The read-modify-write cycle performs a read operation, modifies the data in the arithmetic
logic unit, and writes the data back to the same address. The address strobe ( AS) remains
asserted throughout the entire cycle, making the cycle indivisible. The test and set (TAS)
instruction uses this cycle to provide a signaling capability without deadlock between
processors in a multiprocessing environment. The TAS instruction (the only instruction
MOTOROLA
FC2–FC0, a valid address on the address bus, and drives R/W high (if
neither termination signal is asserted before the falling edge at the end of
S4, the processor inserts wait states (full clock cycles) until either DTACK or
BERR is asserted.
Case 1: DTACK received, with or without BERR .
On the falling edge of the clock entering S7, the processor negates AS,
The write cycle starts in S0. The processor places valid function codes on
a preceding write cycle has left R/W low).
During S1, no bus signals are altered.
On the rising edge of S2, the processor asserts AS and drives R/W low.
During S3, the data bus is driven out of the high-impedance state as the
data to be written is placed on the bus.
At the rising edge of S4, the processor asserts U D S and/or LDS;. The
processor waits for a cycle termination signal (DTACK or BERR ). If
During S5, no bus signals are altered.
During S6, no bus signals are altered.
UDS , and/or LDS . As the clock rises at the end of S7, the processor places
the data bus in the high-impedance state, and drives R/W
high. The device negates DTACK or BERR at this time.
Case 2: BERR received without DTACK .
During state 5 (S5), no bus signals are altered.
During state 6 (S6), no bus signals are altered.
During state 7 (S7), no bus signals are altered.
During state 8 (S8), no bus signals are altered.
AS and UDS/LDS negated. Slave negates BERR. At the end of S9, three-
state data and drive R/W high.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68306 USER'S MANUAL
Go to: www.freescale.com
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