MC68306FC16B Freescale Semiconductor, MC68306FC16B Datasheet - Page 42

no-image

MC68306FC16B

Manufacturer Part Number
MC68306FC16B
Description
IC MPU INTEGRATED 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68306FC16B

Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68306FC16B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68306FC16B
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
STATE 12
STATE 13
STATE 14
STATE 15
STATE 16
STATE 17
STATE 18
STATE 19
STATE 5
STATE 6
STATE 7
STATE 5
STATE 6
STATE 7
STATE 8
STATE 9
3-10
The write portion of the cycle starts in S12. The valid function codes on
FC2–FC0, the address bus lines, AS, and R/W remain unaltered.
During S13, no bus signals are altered.
On the rising edge of S14, the processor drives R/W low.
During S15, the data bus is driven out of the high-impedance state as the
data to be written are placed on the bus.
At the rising edge of S16, the processor asserts UDS /LDS . The processor
waits for D T A C K or BERR . If neither termination signal is asserted
before the falling edge at the close of S16, the processor inserts wait states
(full clock cycles) until either DTACK or BERR is asserted.
Case W1: DTACK with or without BERR .
During S17, no bus signals are altered.
During S18, no bus signals are altered.
On the falling edge of the clock entering S19, the processor negates AS and
UDS /LDS . As the clock rises at the end of S19, the processor
places the data bus in the high-impedance state, and drives
R/W high. The device negates DTACK or BERR at this time.
Case R2: DTACK and BERR on read.
During S5, no bus signals are altered.
AS and U D S /LDS are negated. The cycle terminates without the write
portion.
Case R3: BERR only on read.
During S5, no bus signals are altered.
During S7, no bus signals are altered.
During S8, no bus signals are altered.
AS and U D S /LDS are negated. The cycle terminates without the write
portion.
Case W2: BERR only on write.
During S6, no bus signals are altered, and data from the device is ignored.
During S6, no bus signals are altered..
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68306 USER'S MANUAL
Go to: www.freescale.com
MOTOROLA

Related parts for MC68306FC16B