MC68306FC16B Freescale Semiconductor, MC68306FC16B Datasheet - Page 73

• Manufacturer Part Number: MC68306FC16B
• Description: IC MPU INTEGRATED 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68306FC16B

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

4.3.3 Notation Conventions
Table 4-3 lists the notation conventions used in this manual unless otherwise specified.
MOTOROLA
If <condition>
else <operations>
then <operations>
<operand>tested
sign-extended
<operand> 10
Ax, Ay
Dr, Dq
Dx, Dy
Rx, Ry
TRAP
STOP
Dh, Dl
<op>
BR
Dn
Du
Rn
¯ ˘
An
Dc
Xn
V
+
–
~
˘
Arithmetic addition or postincrement indicator.
Arithmetic subtraction or predecrement indicator.
Arithmetic multiplication.
Arithmetic division or conjunction symbol.
Invert; operand is logically complemented.
Logical AND
Logical OR
Logical exclusive OR
Source operand is moved to destination operand.
Two operands are exchanged.
Any double-operand operation.
Operand is compared to zero and the condition codes are set appropriately.
Equivalent to Format
˘ (SSP); SSP – 2 ˘ SSP; (Vector) ˘ PC
Enter the stopped state, waiting for interrupts.
The operand is BCD; operations are performed in decimal.
Test the condition. If true, the operations after “then” are performed. If the condition is false
and the optional “else” clause is present, the operations after “else” are performed. If the
condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc
instruction description as an example.
Any Address Register n (example: A3 is address register 3)
Source and destination address registers, respectively.
Base Register—An, PC, or suppressed.
Data register D7–D0, used during compare.
Data registers high- or low-order 32 bits of product.
Any Data Register n (example: D5 is data register 5)
Data register’s remainder or quotient of divide.
Data register D7–D0, used during update.
Source and destination data registers, respectively.
Any Address or Data Register
Any source and destination registers, respectively.
Index Register—An, Dn, or suppressed.
All bits of the upper portion are made equal to the high-order bit of the lower portion.
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-3. Notation Conventions
Single and Double Operand Operations
MC68306 USER'S MANUAL
Go to: www.freescale.com
Register Specification
Offset Word ˘ (SSP); SSP – 2 ˘ SSP; PC ˘ (SSP); SSP – 4 ˘ SSP; SR
Other Operations
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