MPC8313CVRAFFB Freescale Semiconductor, MPC8313CVRAFFB Datasheet - Page 94

• Manufacturer Part Number: MPC8313CVRAFFB
• Description: IC MPU POWERQUICC II PRO 516PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CVRAFFB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 333MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8313E-RDB
• Maximum Clock Frequency: 333 MHz
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Program Memory Type: EEPROM/Flash
• For Use With: MPC8313E-RDB - BOARD PROCESSOR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document Revision History
23 Document Revision History
Table 73
94
Number
Rev.
2.2
2.1
3
2
provides a revision history for this hardware specification.
01/2009
12/2008
10/2008
12/2008
Date
MPC8313E PowerQUICC
•
• Made cross-references active for sections, figures, and tables.
• Added Figure 2, after Table 2 and renumbered the following figures.
• Added Note “The information in this document is accurate for revision 1.0, and 2.x and later. See
• Added part numbering details for all the silicon revisions in Table 74.
• Changed V
• Added a row for V
• Added a column for maximum power dissipation in low power mode for Rev 2.x or later silicon in
• Added a column for Power Nos for Rev 2.x or later silicon and added a row for 400 MHz in Table 4.
• Removed footnote, “These are preliminary estimates.” from Table 4.
• Added Table 21 for DDR AC Specs on Rev 2.x or later silicon.
• Added Section 9, “High-Speed Serial Interfaces (HSSI).”
• Added LFWE, LFCLE, LFALE, LOE, LFRE, LFWP, LGTA, LUPWAIT, and LFRB in Table 63.
• In Table 39, added note 2: “This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt
• Removed mentions of SGMII (SGMII has separate specs) from Section 8.1, “Enhanced
• Corrected Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC)
• Added ZQ package to ordering information In Table 74 and Section 19.1, “Package Parameters for
• Removed footnotes 5 and 6 from Table 1 (left over when the PCI undershoot/overshoot voltages and
• Removed SD_PLL_TPD (T2) and SD_PLL_TPA_ANA (R4) from Table 63.
• Added Section 8.3, “SGMII Interface Electrical Characteristics.” Removed Section 8.5.3 SGMII DC
• Removed “HRESET negation to SRESET negation (output)” spec and changed “HRESET/SRESET
• Clarified POR configuration signal specs to “Time for the device to turn off POR configuration signal
• Added Section 24.2, “Part Marking,” and Figure 62.
Table
Section 24.1, “Part Numbers Fully Addressed by this Document,” before Section 1, “Overview.”
Table 6.
Clock Select] field determines the clock frequency of the Mgmt Clock EC_MDC.)”
Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps)—MII/RMII/RGMII/SGMII/RTBI
Electrical Characteristics.”
(10/100/1000 Mbps)—MII/RMII/RGMII/SGMII/RTBI Electrical Characteristics,” to state that
RGMII/RTBI interfaces only operate at 2.5 V, not 3.3 V.
the MPC8313E TEPBGAII” (applicable to both silicon rev. 1.0 and 2.1)
maximum AC waveforms were removed from Section 2.1.2, “Power Supply Voltage Specification”).
Electrical Characteristics.
assertion (output)” spec to “HRESET assertion (output)” in Table 10.
drivers with respect to the assertion of HRESET” and “Time for the device to turn on POR
configuration signal drivers with respect to the negation of HRESET” in Table 10.
74, in column aa, changed to AG = 400 MHz.
IH
from 2.7 V to 2.4 V in Table 7.
Table 73. Document Revision History
IH
level for Rev 2.x or later in Table 45.
™
II Pro Processor Hardware Specifications, Rev. 3
Substantive Change(s)
Freescale Semiconductor