CS42436-DMZ Cirrus Logic Inc, CS42436-DMZ Datasheet - Page 31

• Manufacturer Part Number: CS42436-DMZ
• Description: IC CODEC 108DB 192KHZ 52-MQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42436-DMZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 6 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 52-MQFP, 52-PQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 6
• No. Of Dacs: 6
• No. Of Input Channels: 6
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Sampling Rate: 200kSPS
• Ic Interface Type: I2C
• Package: 52MQFP
• Adc/dac Resolution: 24 Bit
• Number Of Channels: 6ADC /6 DAC
• Number Of Dacs: 6
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1613

DS647F2
No
H/W pins setup to
1. VQ = VA/2.
2. Aout bias = VA/2.
3. No audio signal generated.
Hardware Mode
desired settings.
Valid MCLK
Applied?
1. VQ = VA/2.
2. Aout = HI-Z.
3. No audio signal generated.
4. Control Port Registers reset
to default.
No
Power-Down (Power Applied)
Yes
Analog Output Mute
1. VQ = ?
2. Aout bias = ?
3. No audio signal
generated.
Access Detected?
Control Port
RST = Low?
Control Port
No Power
Accessed
Figure 11. Audio Output Initialization Flow Chart
No
ERROR: MCLK/LRCK ratio change
Registers setup to
Software Mode
desired settings.
Valid MCLK
Yes
Applied?
Yes
ERROR: Power removed
Yes
No
RST = Low
1. VQ = VA/2.
2. Aout bias = VA/2.
3. Audio signal generated per register settings.
No
1. VQ = VA/2.
2. Aout bias = VQ.
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
Sub-Clocks Applied
Normal Operation
2000 LRCK delay
PDN bit = '1'b?
MCLK/LRCK
1. VQ = VA/2.
2. Aout bias = VA/2 + last audio sample.
3. No audio signal generated.
Power-Up
Ratio?
Valid
Yes
No
ERROR: MCLK removed
Analog Output Freeze
Yes
1. VQ = VA/2.
2. Aout bias = Hi-Z.
3. No audio signal generated.
4. Control Port Registers retain
settings.
PDN bit set
to '1'b
Power-Down
CS42436
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