CS42436-DMZ Cirrus Logic Inc, CS42436-DMZ Datasheet - Page 49

• Manufacturer Part Number: CS42436-DMZ
• Description: IC CODEC 108DB 192KHZ 52-MQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42436-DMZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 6 / 6
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 52-MQFP, 52-PQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 6
• No. Of Dacs: 6
• No. Of Input Channels: 6
• No. Of Output Channels: 6
• Adc / Dac Resolution: 24bit
• Sampling Rate: 200kSPS
• Ic Interface Type: I2C
• Package: 52MQFP
• Adc/dac Resolution: 24 Bit
• Number Of Channels: 6ADC /6 DAC
• Number Of Dacs: 6
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1613

DS647F2
7.12
7.12.1 Invert Signal Polarity (INV_AINX)
7.13
7.13.1 CLOCK ERROR (CLK ERROR)
7.13.2 ADC Overflow (ADCX_OVFL)
7.14
Reserved
Reserved
Reserved
7
7
7
ADC Channel Invert (Address 17h)
Status (Address 19h) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated
mask register will always be “0” in this register.
Status Mask (Address 1Ah)
Default = 0000
Function:
The bits of this register serve as a mask for the error sources found in the register
(Read Only)” on page
affect the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not
affect status register. The bit positions align with the corresponding bits in the Status register.
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
Default = x
Function:
Indicates an invalid MCLK to FS ratio. This status flag is set to “Level Active Mode” and becomes active
during the error condition. See
Default = x
Function:
Indicates that there is an over-range condition anywhere in the CS42436 ADC signal path of each of the
associated ADC’s.
Reserved
Reserved
Reserved
6
6
6
Reserved
Reserved
INV_AIN6
49. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will
5
5
5
“System Clocking” on page 33
Reserved
Reserved
INV_AIN5
4
4
4
CLK Error_M
CLK Error
INV_AIN4
3
3
3
ADC3_OV
ADC3_OVFL
for valid clock ratios.
FL_M
INV_AIN3
2
2
2
ADC2_OVFL_M
ADC2_OVFL
INV_AIN2
1
1
“Status (Address 19h)
1
ADC1_OVFL_M
CS42436
ADC1_OVFL
INV_AIN1
0
0
0
49