LTC4259ACGW-1#PBF Linear Technology, LTC4259ACGW-1#PBF Datasheet - Page 13

• Manufacturer Part Number: LTC4259ACGW-1#PBF
• Description: IC CTRLR POE QUAD AC DISC 36SSOP
• Manufacturer: Linear Technology

Specifications of LTC4259ACGW-1#PBF

• Controller Type: Power over Ethernet Controller (POE)
• Interface: I²C
• Voltage - Supply: 3 V ~ 4 V
• Current - Supply: 2.5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Linear Misc Type: Negative Voltage
• Family Name: LTC4259A
• Package Type: SSOP
• Operating Supply Voltage (min): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER FU CTIO S
Detect/Class Enable (Address 14h): Detection and Clas-
sification Enable, Read/Write. The lower four bits of this reg-
ister enable the detection circuitry at the corresponding port
if that port is in Auto or Semiauto mode. The upper four bits
enable the classification circuitry at the corresponding port
if that port is in Auto or Semiauto mode. In manual mode,
setting a bit in this register will cause the LTC4259A-1 to
perform one classification or detection cycle on the corre-
sponding port. Writing to the Detect/Class Restart PB (18h)
has the same effect without disturbing the Detect/Class
Enable bits for other ports.
Timing Config (Address 16h): Global Timing Configuration,
Read/Write. Bits 0-1 program t
a port is automatically tuned off after the PD is removed.
The LTC4259A-1 can be programmed to monitor whether
port current is below I
is high (AC disconnect). Bits 2-3 program t
during which a port’s current can exceed I
being turned off. If the current is still above I
the LTC4259A-1 will indicate a t
off. Bits 4-5 program t
overcurrent condition during port power-on is considered
a t
t
ant with IEEE 802.3af and may double or quadruple the
energy dissipated by the external MOSFETs during fault con-
ditions. Bits 6-7 are reserved and should be read/written
as 0. See Electrical Characteristics for timer bit encoding.
Also see the Applications Information for descriptions of
t
Misc Config (Address 17h): Miscellaneous Configuration,
Read/Write. Bit 5 is the Osc Fail Mask; it is set by default.
When the Osc Fail Mask bit is clear, it prevents a failure on
the OSCIN pin from setting the Osc Fail bit and causing a
Supply Event Interrupt. Setting bit 7 enables the INT pin.
If this bit is reset, the LTC4259A-1 will not pull down the
INT pin in any condition nor will it respond to the Alert Re-
sponse Address. This bit is set by default.
Pushbutton Registers
Note Regarding Pushbutton Registers: “Pushbutton” reg-
isters are specialized registers that trigger an event when
a 1 is written to a bit; writing a 0 to a bit will do nothing. Unlike
a standard read/write register, where setting a single bit
ICUT
START
START
and t
, t
fault and the port is turned off. Note that using the
ICUT
START
, DC and AC disconnect timing.
times other than the default is not compli-
U
MIN
START
(DC connect) or port impedance
, the time duration before an
DIS
U
ICUT
, the time duration before
fault and turn the port
CUT
CUT
ICUT
after t
without it
, the time
ICUT
,
involves reading the register to determine its status, set-
ting the appropriate bit in software and writing back the
entire register, a pushbutton register allows a single bit to
be written without knowing or affecting the status of the
other bits in the register. Pushbutton registers are write-
only and will return 00h if read.
Det/Class Restart PB (Address 18h): Detection/Classifi-
cation Restart Pushbutton Register, Write Only. Writing a
1 to any bit in this register will start or restart a single
detection or classification cycle at the corresponding port
in Manual mode. It can also be used to set the correspond-
ing bits in the Detect/Class Enable register (address 14h)
for ports in auto or semiauto mode. The lower 4 bits affect
detection on each port while the upper 4 bits affect
classification.
Power Enable PB (Address 19h): Power Enable Pushbutton
Register, Write Only. The lower four bits of this register set
the Power Enable bit in the corresponding Port Status reg-
ister; the upper four bits clear the corresponding Power
Enable bit. Setting or clearing the Power Enable bits via this
register will turn on or off the power in any mode except
shutdown, regardless of the state of detection or classifi-
cation. Note that t
enabled) will still turn off power if they occur.
The Power Enable bit cannot be set if the port has turned
off due to a t
yet counted back to zero. See Applications Information for
more information on t
Clearing the Power Enable bits with this register also
clears the detect and fault event bits, the Port Status
register, and the Detection and Classification Enable bits
for the affected port(s).
Reset PB (Address 1Ah): Reset Pushbutton, Write Only.
Bits 0-3 reset the corresponding port by clearing the power
enable bit, the detect and fault event bits, the status regis-
ter and the detection and classification enable bits for that
port. Bit 4 returns the entire LTC4259A-1 to the power-on
reset state; all ports are turned off, the AUTO pin is reread
and all registers are returned to their power-on defaults,
except V
setting it has no effect. Setting bit 6 releases the Interrupt
pin if it is asserted without affecting the Event registers or
the Interrupt register. When the INT pin is released in this
DD
UVLO, which remains cleared. Bit 5 is reserved;
ICUT
or t
ICUT
START
ICUT
, t
START
fault and the t
timing.
and disconnect events (if
LTC4259A-1
ICUT
timer has not
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