LTC4259ACGW-1#PBF Linear Technology, LTC4259ACGW-1#PBF Datasheet - Page 27

• Manufacturer Part Number: LTC4259ACGW-1#PBF
• Description: IC CTRLR POE QUAD AC DISC 36SSOP
• Manufacturer: Linear Technology

Specifications of LTC4259ACGW-1#PBF

• Controller Type: Power over Ethernet Controller (POE)
• Interface: I²C
• Voltage - Supply: 3 V ~ 4 V
• Current - Supply: 2.5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Linear Misc Type: Negative Voltage
• Family Name: LTC4259A
• Package Type: SSOP
• Operating Supply Voltage (min): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
time using standard I
1 is sending a 1 and reads a 0 on the SDAIN pin on the
rising edge of SCL, it assumes another device with a lower
address is sending and the LTC4259A-1 immediately
aborts its transfer and waits for the next ARA cycle to try
again. If transfer is successfully completed, the LTC4259A-
1 will stop pulling down the INT pin. When the INT pin is
released in this way or if a 1 is written into the Clear
Interrupt pin bit (bit 6 of register 1Ah), the condition
causing the LTC4259A-1 to pull the INT pin down must be
removed before the LTC4259A-1 will be able to pull INT
down again. This can be done by reading and clearing the
event registers or by writing a 1 into the Clear All Interrupts
bit (bit 7 of register 1Ah). The state of the INT pin can only
change between I
or new interrupts are generated after a transaction com-
pletes and before new I
mences. Periodic polling of the alert response address can
be used instead of the INT pin if desired. If any device
acknowledges the alert response address, then the INT
line, if connected, would have been low.
System Software Strategy
Control of the LTC4259A-1 hinges on one decision, the
LTC4259A-1’s operating mode. The three choices are
described under Operating Modes. In Auto mode the
LTC4259A-1 can operate autonomously without direc-
tion from a host controller. Because LTC4259A-1s run-
ning in Auto mode will power every valid PD connected to
them, the PSE must have 15.4W/port available. To reduce
the power requirements of the –48V supply, PSE systems
can track power usage, only turning on ports when
sufficient power is available. The IEEE describes this as a
power allocation algorithm and places two limitations: the
PSE shall not power a PD unless it can supply the
guaranteed power for that PD’s class (see Table 2) and
power allocation may not be based solely on a history of
each PD’s power consumption. In order for a PSE to
implement power allocation, the PSE’s processor/con-
troller must control whether ports are powered—the
LTC4259A-1 cannot be allowed to operate in Auto mode.
Semiauto mode fits the bill as the LTC4259A-1 automati-
cally detects and classifies PDs, then makes this informa-
tion available to the host controller, which decides to
2
C transactions, so an interrupt is cleared
U
2
C bus arbitration. If the LTC4259A-
U
2
C bus communication com-
W
U
apply power or not. Operating the LTC4259A-1 in Manual
mode also lets the controller decide whether to power the
ports but the controller must also control detection and
classification. If the host controller operates near the limit
of its computing resources, it may not be able to guide a
Manual mode LTC4259A-1 through detect, class and port
turn-on in less than the IEEE mandated maximum of
950ms.
In a typical PSE, the LTC4259A-1s will operate in Semiauto
mode as this allows the controller to decide to power a
port without unduly burdening the controller. With an
interrupt mask of F4h, the LTC4259A-1 will signal to the
host after it has successfully detected and classed a PD,
at which point the host can decide whether enough power
is available and command the LTC4259A-1 to turn that
port on. Similarly, the LTC4259A-1 will generate inter-
rupts when a port’s power is turned off. By reading the
LTC4259A-1’s interrupt register, the host can determine
if a port was turned off due to overcurrent (t
faults) or because the PD was removed (Disconnect
event). The host then updates the amount of available
power to reflect the power no longer consumed by the
disconnected PD. Setting the MSB of the interrupt mask
causes the LTC4259A-1 to communicate fault conditions
caused by failures within the PSE, so the host does not
need to poll to check that the LTC4259A-1s are operating
properly. This interrupt driven system architecture pro-
vides the controller with the final say on powering ports
at the same time, minimizing the controller’s computation
requirements because interrupts are only generated when
a PD is detected or on a fault condition.
The LTC4259A-1 can also be used to power older powered
Ethernet devices that are not 802.3af compliant and may
be detected with other methods. Although the LTC4259A-
1 does not implement these older detection methods
automatically, if software or external circuitry can detect
the noncompliant devices, the host controller may com-
mand the LTC4259A-1 to power the port, bypassing IEEE
compliant detection and classification and sending power
to the noncompliant device.
LTC4259A-1
START
27
or t
4259a1fa
ICUT